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Cavium CN5840-900 NSP |
![octeon plus chip.png](/w/images/thumb/f/f8/octeon_plus_chip.png/200px-octeon_plus_chip.png) |
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Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN5840-900 NSP |
Part Number | CN5840-900BG1521-NSP |
Market | Network |
Introduction | October 9, 2006 (announced) February, 2007 (launched) |
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Family | OCTEON Plus |
Series | CN58xx |
Frequency | 900 MHz |
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ISA | MIPS64 (MIPS) |
Microarchitecture | cnMIPS |
Process | 90 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
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Max SMP | 1-Way (Uniprocessor) |
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Package | FCBGA-1521 (BGA) |
Ball Count | 1521 |
Interconnect | BGA-1521 |
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CN5840-900 NSP is a 64-bit octa-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2007. This processor, which incorporates eight cnMIPS cores, operates at 900 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, RegEx, compression/decompression, and TCP acceleration.
Cache
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
![hierarchy icon.svg](/w/images/thumb/e/e4/hierarchy_icon.svg/75px-hierarchy_icon.svg.png) |
Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
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L1$ | 384 KiB 393,216 B 0.375 MiB
| L1I$ | 256 KiB 262,144 B 0.25 MiB
| 8x32 KiB | 64-way set associative | |
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L1D$ | 128 KiB 131,072 B 0.125 MiB
| 8x16 KiB | 64-way set associative | |
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| L2$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB
| | | 1x2 MiB | 8-way set associative | |
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Memory controller
[Edit/Modify Memory Info]
![ram icons.svg](/w/images/thumb/a/af/ram_icons.svg/75px-ram_icons.svg.png) |
Integrated Memory Controller
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Max Type | DDR2-800 |
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Supports ECC | Yes |
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Controllers | 1 |
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Channels | 1 |
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Width | 128 bit |
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Max Bandwidth | 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s
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Bandwidth |
Single 11.92 GiB/s
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Expansions
Networking
Hardware Accelerators
[Edit/Modify Accelerators Info]
![hardware accel icon.svg](/w/images/thumb/b/b0/hardware_accel_icon.svg/75px-hardware_accel_icon.svg.png) |
Hardware Accelerators
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Encryption | Hardware Implementation | Yes |
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Types | DES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI |
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RegEx | RegEx | Yes |
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Features | 32 Engines |
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Compression | Compression | Yes |
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Decompression | Yes |
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Block diagram
Datasheet