From WikiChip
Am486DX2-80SV8B - AMD
Edit Values | |
Am486DX2-80SV8B | |
General Info | |
Designer | AMD |
Manufacturer | AMD |
Model Number | Am486DX2-80SV8B |
Part Number | A80486DX2-80SV8B |
Introduction | 1995 (announced) March, 1996 (launched) |
Shop | Amazon |
General Specs | |
Family | Am486 |
Series | Am486DX2S |
Frequency | 80 MHz |
Bus type | FSB |
Bus speed | 40 MHz |
Bus rate | 40 MT/s |
Clock multiplier | 2 |
Microarchitecture | |
Microarchitecture | 80486 |
Core Name | Am486DX2S |
Process | 500 nm |
Technology | CMOS |
Word Size | 32 bit |
Cores | 1 |
Max Memory | 4 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 3.3 V ± 0.3 V |
OP Temperature | 0 °C – 85 °C |
Am486DX2-80SV8B was an Enhanced Am486 microprocessor introduced by AMD in 1996. This processor had a clock multiplier of 2 having base frequency of 80 MHz with a bus frequency of 40 MHz. This "Enhanced" Am486 includes some other features such as SMM, stop-clock control, and write-back cache.
Contents
Cache
- Main article: 80486 § Cache
Cache Info [Edit Values] | ||
L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-back policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- Stop-clock control
- System Management Mode (SMM)
Documents
See also
Facts about "Am486DX2-80SV8B - AMD"
has feature | System Management Mode + |
l1$ description | 4-way set associative + |
l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |