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Alpha 21064 µarch
General Info
Arch Type	CPU
Designer	DEC
Manufacturer	DEC
Introduction	November 20, 1992
Process	0.75 µm, 0.675 µm
Core Configs	1
Pipeline
Type	Superscalar
OoOE	No
Speculative	Yes
Reg Renaming	No
Stages	7-12
Decode	2-way
Instructions
ISA	Alpha
Cache
L1I Cache	8 KiB/core direct-mapped
L1D Cache	8 KiB/core direct-mapped
L2 Cache	0.125-16 MiB/motherboard
Succession
Alpha 21164 Alpha 21064A

Alpha 21064 was the first Alpha microarchitecture designed by DEC and introduced in 1992.

Etymology

The microarchitecture name Alpha 21064 is composed of both the ISA and the implementation. In particular, the "Alpha" refers to DEC's Alpha AXP instruction set architecture while the "21064" refers to a "21st century"-ready 64-bit "generation 0" microarchitecture.

Release Dates

Tape-out for the Alpha 21064 occurred on July 14, 1991. First parts were available on August 30 and a successful boot-up took place on November 3 the same year. DEC first announced their 21064 architecture in February of 1992. Alpha 21064-based chips were first introduced during COMDEX on November 20, 1992.

Process Technology

See also: 0.75 µm process

Alpha 21064 was manufactured on DEC's CMOS-4, their then-newest 0.75 µm process. The process offered three levels of aluminum interconnects and a nominal 3.3 V power supply. Note that prior to the introduction of the 21064, DEC produced early "assistance" samples for software developers which were manufactured on an older CMOS-3 process (1 µm). For that reason those chips also had reduced cache amount, in addition to no FPU support.

Compatibility

Vendor	OS	Version	Notes
Microsoft	Windows	Windows NT	Support
DEC	OpenVMS	OpenVMS AXP V1.0	Initial OpenVMS support
DEC	OSF/1 AXP	1.0
Novell	Netware	3.2

Architecture

The 21064 was designed to be a very fast implementation of DEC's Alpha

• 0.75 µm process
• 150-200 MHz (6.6-5 nm cycles)
• FP Unit
  • Support for IEEE 754
  • Support for VAX floating point
• System bus
  • Separate data & address buses
  • 64/128-bit data bus
• Directly serial ROM interface
• Pipeline
  • 2-way instruction issue to A-/E-/F- Boxes
  • Integer Execution Unit
    • 32-entry integer register file
    • 64-bit integers operations
    • 7-stage pipeline
  • FP Execution Unit
    • 32-entry FP register file
    • 10-stage pipeline
• Memory subsystem
  • 4-entry, 32-byte/entry write buffer

Memory Hierarchy

• Cache
  • L1D Cache:
    • 8 KiB direct-mapped
    • 32-byte line size
    • 32-byte fill
    • write-through policy
  • L1I Cache:
    • 8 KiB direct-mapped
    • 32-byte line size
    • 32-byte fill
    • 64 ASNs
  • L2 Cache:
    • 0.125-16 MiB
    • Implemented externally on the motherboard
    • Direct on-chip pin interface
  • DRAM
    • Virtual address size
      • 64-bit, 43-bit implemented
    • Physical address size
      • 34-bit implemented

Alpha 21064 TLB consists of dedicated level one TLB for instruction cache and another one for data cache.

• TLBs
  • ITLB
    • 8 KiB, 64 KiB, 256 KiB, 4 MiB page sizes
    • 32-entry, fully-associative
  • DTLB
    • 8 KiB page translations:
      • 8-entry, fully-associative
    • 4 MiB page translations:
      • 4-entry, fully-associative

Die

• 30 W power dissipation @ 200 MHz, 3.3 V power supply
• 0.75 µm process
• 3 metal layers
• 1,680,000 transistors
• 13.9 mm x 16.8 mm
• 233.52 mm² die size
• PGA-431
  • 291 signal pins
  • 140 power/ground rail pins

References

• McLellan, Edward. "The Alpha AXP architecture and 21064 processor." IEEE Micro 13.3 (1993): 36-47.