Cavium OCTEON
CN38xx
Developer	Cavium
Manufacturer	TSMC
Type	System on chips
Introduction	September 13, 2004 (announced) June 1, 2005 (launch)
Architecture	MIPS64 R2 network SoCs
ISA	MIPS64
µarch	cnMIPS
Word size	64 bit 8 octets 16 nibbles
Process	130 nm 0.13 μm 1.3e-4 mm
Technology	CMOS
Clock	400 MHz-600 MHz
Package	FCBGA-1521, HSBGA-868
Socket	BGA-1521, BGA-868
Succession
	→
	OCTEON II

OCTEON was a family of 64-bit multi-core MIPS microprocessors designed by Cavium for networking devices.

Overview

The original OCTEON family of network-oriented microprocessors were announced in September of 2004. These chips are based on Cavium's newly announced microarchitecture, cnMIPS, announced the same day. The cnMIPS design is a fully compliant MIPS64 revision 2 implementation. OCTEON chips are found in many enterprise an data center network servers, routers, and switches as well as various high-end residential routers.

Architecture

Main article: cnMIPS µarch

The cnMIPS microarchitecture is a fully-custom design implementing the MIPS64 revision 2 ISA on TSMC's 130 nm process. Due to the specific nature of the applicatons running, an FPU was omitted. Instead, Cavium opted to incorporate a wide array of hardware accelerators for network applications (L3 to L7) including support for compression/decompression algorithms (e.g.GZIP), and security/crypto algorithms (e.g. DES, AES, MD5, and SHA1).

Members

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Datasheet

• OCTEON CN30XX Processors Product Brief
• OCTEON CN31XX Single- and Dual-Core Product Brief
• OCTEON CN38XX /CN36XX 4 to 16-Core Product Brief