Kirin - HiSilicon

Kirin

Kirin Logo
Developer	HiSilicon, ARM Holdings
Manufacturer	TSMC
Type	System on chips
Introduction	2013 (announced) 2014 (launch)
Architecture	Performance mobile ARM SOCs
ISA	ARM
µarch	Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A72, Cortex-A73, Cortex-A76, Cortex-A77
Word size	32 bit 4 octets 8 nibbles , 64 bit 8 octets 16 nibbles
Process	28 nm 0.028 μm 2.8e-5 mm , 16 nm 0.016 μm 1.6e-5 mm , 14 nm 0.014 μm 1.4e-5 mm , 12 nm 0.012 μm 1.2e-5 mm , 10 nm 0.01 μm 1.0e-5 mm , 7 nm 0.007 μm 7.0e-6 mm , 5 nm 0.005 μm 5.0e-6 mm
Technology	CMOS
Clock	356 MHz-3,130 MHz
Succession
←
K3

Kirin is a family of 32-bit and 64-bit mobile ARM performance SoCs introduced by HiSilicon in 2014 as a successor to the K3 series.

Overview

HiSilicon has always been the integrated circuit arm of Huawei, developing various ICs and embedded microprocessors for their consumer electronics. It wasn't until 2008 with the introduction of the K3 family that HiSilicon started focusing on developing in-house high-performance microprocessors for the mobile market. In late 2013 HiSilicon introduced the Kirin family which featured their flagship high-performance mobile microprocessors found in their high-end phones and tablets.

Over the last couple of years, the Kirin family grew to include various mid-range performance models in addition to their high-end performance flagship processors. Latest models often utilize ARM's latest cores fabricated on TSMC's latest technology node.

Members

designer	HiSilicon + and ARM Holdings +
first announced	2013 +
first launched	2014 +
full page name	hisilicon/kirin +
instance of	system on a chip family +
instruction set architecture	ARM +
main designer	HiSilicon +
manufacturer	TSMC +
microarchitecture	Cortex-A9 +, Cortex-A15 +, Cortex-A53 +, Cortex-A72 +, Cortex-A73 +, Cortex-A76 + and Cortex-A77 +
name	Kirin +
process	28 nm (0.028 μm, 2.8e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 12 nm (0.012 μm, 1.2e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +
technology	CMOS +
word size	32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) +

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