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Difference between revisions of "amd/epyc embedded/3251"
< amd‎ | epyc embedded

(Added missing data. TDP revised to 55 W in "AMD EPYC™ Embedded 3000 Family" Rev. E.)
Line 11: Line 11:
 
|first announced=February 21, 2018
 
|first announced=February 21, 2018
 
|first launched=February 21, 2018
 
|first launched=February 21, 2018
−
|release price=$315.00
+
|last order=2028
 +
|release price=$315
 
|family=EPYC Embedded
 
|family=EPYC Embedded
 
|series=3000
 
|series=3000
 +
|locked=Yes
 
|frequency=2,500 MHz
 
|frequency=2,500 MHz
 
|turbo frequency1=3,100 MHz
 
|turbo frequency1=3,100 MHz
Line 24: Line 26:
 
|core family=23
 
|core family=23
 
|core model=1
 
|core model=1
 +
|core stepping=B2
 +
|cpuid=0x00800F12
 
|process=14 nm
 
|process=14 nm
 
|transistors=4,800,000,000
 
|transistors=4,800,000,000
Line 38: Line 42:
 
|package module 1={{packages/amd/package sp4r2}}
 
|package module 1={{packages/amd/package sp4r2}}
 
}}
 
}}
−
'''EPYC Embedded 3251''' is a {{arch|64}} [[octa-core]] [[x86]] embedded microprocessor introduced by [[AMD]] in early [[2018]] for dense servers and edge devices. Fabricated on a [[14 nm process]] based on the {{amd|Zen|Zen microarchitecture|l=arch}}, this chip operates at 2.5 GHz with a TDP of 55 W and a {{amd|precision boost|turbo frequency}} of 3.1 GHz. The 3251 supports up to 512 GiB of dual-channel DDR4-2666 memory.
+
'''EPYC Embedded 3251''' is a {{arch|64}} [[octa-core]] [[x86]] embedded microprocessor introduced by [[AMD]] in early [[2018]] for dense servers and edge devices. This processor has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[GlobalFoundries]] [[14 nm#GlobalFoundries|14&nbsp;nm]] process. It operates at 2.5 GHz with a {{abbr|TDP}} of 55 W and a {{amd|precision boost|turbo frequency}} of up to 3.1 GHz. The 3251 supports up to 512 GiB of dual-channel DDR4-2666 memory.
−
 
 
  
 
== Cache ==
 
== Cache ==
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|l1 cache=768 KiB
 
|l1 cache=768 KiB
 
|l1i cache=512 KiB
 
|l1i cache=512 KiB
−
|l1i break=8x64 KiB
+
|l1i break=8 × 64 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
 
|l1d cache=256 KiB
 
|l1d cache=256 KiB
−
|l1d break=8x32 KiB
+
|l1d break=8 × 32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d policy=write-back
 
|l1d policy=write-back
 
|l2 cache=4 MiB
 
|l2 cache=4 MiB
−
|l2 break=8x512 KiB
+
|l2 break=8 × 512 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back
 
|l3 cache=16 MiB
 
|l3 cache=16 MiB
−
|l3 break=2x8 MiB
+
|l3 break=2 × 8 MiB
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
Line 69: Line 72:
 
|controllers=2
 
|controllers=2
 
|channels=2
 
|channels=2
−
|max bandwidth=39.74 GiB/s
+
|max bandwidth=42.67 GB/s
−
|bandwidth schan=19.87 GiB/s
+
|bandwidth schan=21.33 GB/s
−
|bandwidth dchan=39.74 GiB/s
+
|bandwidth dchan=42.67 GB/s
 
}}
 
}}
  
 
== Expansions ==
 
== Expansions ==
−
The EPYC Embedded 3251 supports up to 32 PCIe Gen 3 (8 GT/s) lanes. Some of these lanes can be configured as SATA 3 (6 Gb/s) and 10 Gigabit Ethernet ports. Up to 8 SATA ports and four GbE ports are available on this model, as well as four USB 3.1 Gen 1 (5 Gb/s) ports, and the following low speed interfaces: EMMC, eSPI, GPIO, I2C, LPC, SMBus, SPI, UART.
+
The EPYC Embedded 3251 integrates two 8-port, 16-lane PCIe Gen 1/2/3 (8 GT/s) controllers. All lanes are configurable as x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) PCIe links, some lanes alternatively as SATA Gen 1/2/3 (6 Gb/s) or 10 Gbit/s Ethernet ports. Up to eight SATA ports and four GbE ports are available on this model, as well as four USB 3.1 Gen 1 (5 Gb/s) ports, and the following low speed interfaces: {{abbr|eMMC}}, {{abbr|UART}}, {{abbr|LPC}}, {{abbr|SPI/eSPI}}, {{abbr|I<sup>2</sup>C}}, {{abbr|SMBus}}, {{abbr|GPIO}}.
 +
 
 
{{expansions main
 
{{expansions main
 
|
 
|
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|pcie config 3=x4
 
|pcie config 3=x4
 
|pcie config 4=x2
 
|pcie config 4=x2
 +
|pcie config 5=x1
 
}}
 
}}
 
{{expansions entry
 
{{expansions entry
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|sse42=Yes
 
|sse42=Yes
 
|sse4a=Yes
 
|sse4a=Yes
 +
|sse_gfni=No
 
|avx=Yes
 
|avx=Yes
 +
|avx_gfni=No
 
|avx2=Yes
 
|avx2=Yes
−
 
+
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512gfni=No
 +
|avx512vaes=No
 +
|avx512vbmi2=No
 +
|avx512bitalg=No
 +
|avx512vpclmulqdq=No
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
Line 139: Line 163:
 
|clmul=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|f16c=Yes
 +
|bfloat16=No
 
|tbt1=No
 
|tbt1=No
 
|tbt2=No
 
|tbt2=No
 
|tbmt3=No
 
|tbmt3=No
 +
|tvb=No
 
|bpt=No
 
|bpt=No
 
|eist=No
 
|eist=No
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|flex=No
 
|flex=No
 
|fastmem=No
 
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 
|isrt=No
 
|isrt=No
 
|sba=No
 
|sba=No
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|securekey=No
 
|securekey=No
 
|osguard=No
 
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
Line 177: Line 212:
 
|sensemi=Yes
 
|sensemi=Yes
 
|xfr=No
 
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 
}}
 
}}
  
−
== References ==
+
== Bibliography ==
−
* [https://www.amd.com/system/files/documents/updated-3000-family-product-brief.pdf "AMD EPYC™ Embedded 3000 Family"], AMD Publ. #1887102, Rev. E, 2019
+
* [https://ir.amd.com/news-events/press-releases/detail/816/amd-launches-epyc-embedded-and-ryzen-embedded "AMD Launches EPYC™ Embedded and Ryzen™ Embedded Processors for End-to-End “Zen” Experiences from the Core to the Edge"] (Press release). AMD.com. February 21, 2018.
−
* [https://www.amd.com/en/products/specifications/embedded "Embedded Processor Specifications"]. <i>AMD.com</i>. Retrieved October 2020.
+
* {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|file=3000-Family-Product-Brief.pdf|publ=AMD|pid=1887102|date=2018}}
 +
* {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|url=https://www.amd.com/system/files/documents/updated-3000-family-product-brief.pdf|publ=AMD|pid=1887102|rev=E|date=2019}}
 +
* [https://www.amd.com/en/products/specifications/embedded "Embedded Processor Specifications"]. AMD.com. Retrieved October 2020.

Revision as of 05:27, 6 April 2022

Edit Values
EPYC Embedded 3251
General Info
DesignerAMD
ManufacturerGlobalFoundries
Model Number3251
Part NumberPE3251BGR88AF
MarketServer, Embedded
IntroductionFebruary 21, 2018 (announced)
February 21, 2018 (launched)
End-of-life2028 (last order)
Release Price$315
ShopAmazon
General Specs
FamilyEPYC Embedded
Series3000
LockedYes
Frequency2,500 MHz
Turbo Frequency3,100 MHz (1 core),
3,100 MHz (8 cores)
Clock multiplier25
CPUID0x00800F12
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen
Core NameSnowy Owl
Core Family23
Core Model1
Core SteppingB2
Process14 nm
Transistors4,800,000,000
TechnologyCMOS
Die213 mm²
Word Size64 bit
Cores8
Threads16
Max Memory512 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP55 W
Tjunction0 °C – 105 °C
Packaging
Template:packages/amd/package sp4r2

EPYC Embedded 3251 is a 64-bit octa-core x86 embedded microprocessor introduced by AMD in early 2018 for dense servers and edge devices. This processor has CPU cores based on the Zen microarchitecture and is fabricated on a GlobalFoundries 14 nm process. It operates at 2.5 GHz with a TDP of 55 W and a turbo frequency of up to 3.1 GHz. The 3251 supports up to 512 GiB of dual-channel DDR4-2666 memory.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$512 KiB
524,288 B
0.5 MiB
8 × 64 KiB4-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8 × 32 KiB8-way set associativewrite-back
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  8 × 512 KiB8-way set associativewrite-back
L3$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  2 × 8 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem512 GiB
Controllers2
Channels2
Max Bandwidth42.67 GB/s
39.74 GiB/s
40,693.283 MiB/s
42,670 MB/s
0.0388 TiB/s
0.0427 TB/s
Bandwidth
Single 21.33 GB/s
Double 42.67 GB/s

Expansions

The EPYC Embedded 3251 integrates two 8-port, 16-lane PCIe Gen 1/2/3 (8 GT/s) controllers. All lanes are configurable as x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) PCIe links, some lanes alternatively as SATA Gen 1/2/3 (6 Gb/s) or 10 Gbit/s Ethernet ports. Up to eight SATA ports and four GbE ports are available on this model, as well as four USB 3.1 Gen 1 (5 Gb/s) ports, and the following low speed interfaces: eMMC, UART, LPC, SPI/eSPI, I2C, SMBus, GPIO.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 32
Configuration: x16, x8, x4, x2, x1
USBRevision: 3.1
Max Ports: 4
SATARevision: 3.0
Max Ports: 8

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
10GbEYes (Ports: 4)

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology

Bibliography

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc_embedded/3251&oldid=99930"
Facts about "EPYC Embedded 3251 - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC Embedded 3251 - AMD#pcie +
base frequency2,500 MHz (2.5 GHz, 2,500,000 kHz) +
clock multiplier25 +
core count8 +
core family23 +
core model1 +
core nameSnowy Owl +
core steppingB2 +
cpuid0x00800F12 +
designerAMD +
die area213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
familyEPYC Embedded +
first announcedFebruary 21, 2018 +
first launchedFebruary 21, 2018 +
full page nameamd/epyc embedded/3251 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description16-way set associative +
l3$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
last order2028 +
ldateFebruary 21, 2018 +
manufacturerGlobalFoundries +
market segmentServer + and Embedded +
max cpu count1 +
max junction temperature378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth39.74 GiB/s (40,693.283 MiB/s, 42.67 GB/s, 42,670 MB/s, 0.0388 TiB/s, 0.0427 TB/s) +
max memory channels2 +
max sata ports8 +
max usb ports4 +
microarchitectureZen +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number3251 +
nameEPYC Embedded 3251 +
part numberPE3251BGR88AF +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 315.00 (€ 283.50, £ 255.15, ¥ 32,548.95) +
series3000 +
smp max ways1 +
supported memory typeDDR4-2666 +
tdp55 W (55,000 mW, 0.0738 hp, 0.055 kW) +
technologyCMOS +
thread count16 +
transistor count4,800,000,000 +
turbo frequency (1 core)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (8 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +