Revision as of 22:53, 3 April 2022

T52R is a 64-bit single-core x86 embedded microprocessor introduced by AMD in early 2011. This processor is a member of the AMD Embedded G-Series formerly codenamed "eBrazos" with CPU cores based on the Bobcat microarchitecture and is fabricated on a TSMC 40 nm process. The T52R operates at a base frequency of 1.5 GHz with a TDP of 18 W. It supports single-channel DDR3-1333 memory and integrates a Radeon HD 6310 GPU operating at up to 500 MHz.

Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 64 KiB 65,536 B 0.0625 MiB L1I$ 32 KiB 32,768 B 0.0313 MiB 1 × 32 KiB 2-way set associative   L1D$ 32 KiB 32,768 B 0.0313 MiB 1 × 32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1 × 512 KiB 16-way set associative

Memory controller

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	Integrated Memory Controller
	Max Type DDR3-1333 Supports ECC No Controllers 1 Channels 1 Max Bandwidth 10.67 GB/s 9.937 GiB/s 10,175.705 MiB/s 10,670 MB/s 0.0097 TiB/s 0.0107 TB/s

Expansions

"eBrazos" processors integrate one 5-port, 8-lane PCIe Gen 1/2 (5 GT/s) controller. Four GPP lanes are configurable as up to four x4/x2/x1 wide (e.g. 1x2 + 2x1) links, the remaining four lanes are reserved for a UMI link to the chipset. The recommended AMD A50M "Hudson-M1" and A55E "Hudson-E1" controller hubs provide four PCIe Gen 1/2 lanes configurable as up to four x4/x2/x1 links, a 32-bit, 33 MHz PCI interface (A55E only), 6 × SATA Gen 1/2/3 (6 Gb/s), 14 × USB 1.1/2.0, 2 × USB 1.1, a Gb Ethernet MAC (A55E), HDA, LPC, SPI, SMBus, GPIO.

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 2.0 Max Lanes: 4 Configuration: 1x4/2x2/1x2+2x1/4x1

Graphics

This processor integrates an AMD Radeon GPU of the Evergreen series with two compute units based on the TeraScale 2 microarchitecture. It features 80 stream processing units, 8 texture units, 16 Z/Stencil ROP units, and four color ROP units. Decoding of H.264, VC-1, MPEG-2, and DivX/Xvid video streams is accelerated by a UVD 3 engine. Two independent display controllers natively support the DisplayPort 1.1a protocol on two 4-lane DDIs, a Flat Panel Display (LVDS) link on the first port, and a VGA interface with 30 bpp color depth and up to 400 MHz pixel clock. The eDP, DVI, and HDMI protocols are supported with additional components. The maximum display resolution is 2560 × 1600 at 60 Hz, and 1920 × 1200 for the second display, limited by the available memory bandwidth.

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Radeon HD 6310 Designer AMD Execution Units 2 Max Displays 2 Unified Shaders 80 TMUs 8 ROPs 4 Frequency 500 MHz 0.5 GHz 500,000 KHz Max Resolution 2560 × 1600 Output DP, eDP, HDMI, VGA, DVI, LVDS Max Resolution HDMI 1920 × 1080 @60 Hz DVI 1920 × 1200 @60 Hz DP 2560 × 1600 @60 Hz eDP 2048 × 1536 VGA 2560 × 1600 LVDS 1440 × 900 @60 Hz Standards DirectX 11 OpenGL 4.0 OpenCL 1.1 DP 1.1a

Features

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	Supported x86 Extensions & Processor Features
	MMX MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4a Streaming SIMD Extensions 4a x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU AMD-V AMD Virtualization

Bibliography

• "Product Brief: AMD Embedded G-Series APU Platform", AMD Publ. #49282, 2013
• "BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #43170, Rev. 3.13, February 17, 2012
• "Revision Guide for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #47534, Rev. 3.18, February 26, 2013
• Burgess, Brad. "“Bobcat” AMD’s New Low Power x86 Core Architecture", Hot Chips 22, August 24, 2010
• Burgess, Brad et al. (2011). Bobcat: AMD’s Low-Power x86 Processor. IEEE Micro. 31 (2): 16-25. doi:10.1109/MM.2011.2
• Foley, Denis et al. (2011). A Low-Power Integrated x86–64 and Graphics Processor for Mobile Computing Devices. IEEE JSSC. 47 (1): 220-231. doi:10.1109/JSSC.2011.2167776
• Rogers, Aaron; Kaplan, David; Quinnell, Eric; Kwan, Bill (2012). The Core-C6 (CC6) Sleep State of the AMD Bobcat x86 Microprocessor. ACM/IEEE ISLPED 2012. pp. 367-372. doi:10.1145/2333660.2333745
• "AMD Delivers the World's First and Only APU for Embedded Systems" (Press release). AMD.com. January 19, 2011.