Semiconductor & Computer Engineering
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Difference between revisions of "intel/microarchitectures/sapphire rapids"
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== Architecture == | == Architecture == | ||
=== Key changes from {{\\|Ice Lake (server)|Ice Lake}}=== | === Key changes from {{\\|Ice Lake (server)|Ice Lake}}=== | ||
| − | * [[ | + | * [[Intel 7]] (from [[10 nm SuperFIN]]) |
* Core | * Core | ||
** {{\\|Sunny Cove}} '''→''' {{\\|Golden Cove}} | ** {{\\|Sunny Cove}} '''→''' {{\\|Golden Cove}} | ||
Revision as of 22:30, 21 August 2021
| Edit Values | |
| Sapphire Rapids µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2021 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Sapphire Rapids (SPR) is Intel's successor to Ice Lake, a 10 nm microarchitecture for enthusiasts and servers.
History
Sapphire Rapids was first announced during the May 2019 Intel Investor Meeting. Sapphire Rapids is planned to succeed Ice Lake in 2021.
Process Technology
Sapphire Rapids is planned to be manufactured on the Intel 7 process (previously 10nm Enhanced SuperFin (ESF)).
Architecture
Key changes from Ice Lake
- Intel 7 (from 10 nm SuperFIN)
- Core
- New Integration
- Memory
- DDR5 (from DDR4)
- Optane DC DIMMs
- Barlow Pass → Crow Pass
- I/O
- PCIe Gen 5.0 (from Gen 4.0)
- Platform
This list is incomplete; you can help by expanding it.
See also
Facts about "Sapphire Rapids - Microarchitectures - Intel"
| codename | Sapphire Rapids + |
| designer | Intel + |
| first launched | 2021 + |
| full page name | intel/microarchitectures/sapphire rapids + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Sapphire Rapids + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |