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Difference between revisions of "arm holdings/microarchitectures/neoverse v1"
(Zeus) |
(No difference)
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Revision as of 00:03, 26 April 2021
Edit Values | |
Neoverse V1 µarch | |
General Info | |
Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | 2021 |
Process | 7 nm |
Pipeline | |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Neoverse V1 (codename Zeus) is a high-performance ARM microarchitecture designed by ARM Holdings for the high-performance computing market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/neoverse_v1&oldid=98755"
Facts about "Neoverse V1 - Microarchitectures - ARM"
codename | Neoverse V1 + |
designer | ARM Holdings + |
first launched | 2021 + |
full page name | arm holdings/microarchitectures/neoverse v1 + |
instance of | microarchitecture + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Neoverse V1 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |