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Difference between revisions of "intel/microarchitectures/alder lake"
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* Core | * Core | ||
** Hybrid Golden Cove(big core) & Gracemont(small core) microarchitecture | ** Hybrid Golden Cove(big core) & Gracemont(small core) microarchitecture | ||
| + | ** Up to 20% IPC improvements | ||
| + | ** Improved 10 nm node | ||
Revision as of 06:07, 3 February 2021
| Edit Values | |
| Alder Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2021 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Alder Lake (ADL) is Intel's successor to Tiger Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.
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Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Process Technology
History
Architecture
Key changes from Tiger Lake
- Core
- Hybrid Golden Cove(big core) & Gracemont(small core) microarchitecture
- Up to 20% IPC improvements
- Improved 10 nm node
Facts about "Alder Lake - Microarchitectures - Intel"
| codename | Alder Lake + |
| designer | Intel + |
| first launched | 2021 + |
| full page name | intel/microarchitectures/alder lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Alder Lake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |