From WikiChip
Difference between revisions of "intel/microarchitectures/rocket lake"
< intel‎ | microarchitectures

(corrected and added info)
Line 55: Line 55:
 
|l1d per=core
 
|l1d per=core
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
|l2= 1280 KiB
+
|l2=512 KiB
 
|l2 per=core
 
|l2 per=core
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
|l3=3 MiB
+
|l3=2 MiB
 
|l3 per=core
 
|l3 per=core
 
|l3 desc=Up to 16-way set associative
 
|l3 desc=Up to 16-way set associative
Line 66: Line 66:
 
|predecessor=Comet Lake
 
|predecessor=Comet Lake
 
|predecessor link=intel/microarchitectures/comet lake
 
|predecessor link=intel/microarchitectures/comet lake
 +
|successor=Alder Lake
 +
|successor link=intel/microarchitectures/alder_lake
 +
|contemporary=Tiger Lake
 +
|contemporary link=intel/microarchitectures/tiger_lake
 
}}
 
}}
 
'''Rocket Lake''' ('''RKL''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices.
 
'''Rocket Lake''' ('''RKL''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices.

Revision as of 05:18, 14 July 2020

Edit Values
Rocket Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Process14 nm
Core Configs4
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX
Cache
L1I Cache48 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache512 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
L4 Cache128 MiB/package
on Iris Pro GPUs only
Succession
Contemporary
Tiger Lake

Rocket Lake (RKL) is a planned microarchitecture designed by Intel as a successor to Comet Lake for desktops and high-performance mobile devices.


Codenames

Core Description Graphics Target
Rocket Lake S Mainstream performance GT2 Desktop performance to value, AiOs, and minis
Rocket Lake U Ultra-low power GT2 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Brands

Intel is expected to release Rocket Lake under 3 main brand families:

Logo Family General Description Differentiating Features
Cores HT AVX AVX2 TBT ECC
core i3 logo (2015).png Core i3 Low-end Performance
core i5 logo (2015).png Core i5 Mid-range Performance
core i7 logo (2015).png Core i7 High-end Performance

Release Dates

Rocket Lake is expected to be released in Q4 2020 or Q1 2021.

Compatibility

New text document.svg This section is empty; you can help add the missing info by editing this page.

Compiler support

Compiler Arch-Specific Arch-Favorable
ICC -march=skylake -mtune=skylake
GCC -march=skylake -mtune=skylake
LLVM -march=skylake -mtune=skylake
Visual Studio /arch:AVX2 /tune:skylake

CPUID

New text document.svg This section is empty; you can help add the missing info by editing this page.

Architecture

Key changes from Coffee Lake

New text document.svg This section is empty; you can help add the missing info by editing this page.

See also