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Difference between revisions of "intel/microarchitectures/rocket lake"
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|l1d per=core | |l1d per=core | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
− | |l2= | + | |l2=512 KiB |
|l2 per=core | |l2 per=core | ||
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
− | |l3= | + | |l3=2 MiB |
|l3 per=core | |l3 per=core | ||
|l3 desc=Up to 16-way set associative | |l3 desc=Up to 16-way set associative | ||
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|predecessor=Comet Lake | |predecessor=Comet Lake | ||
|predecessor link=intel/microarchitectures/comet lake | |predecessor link=intel/microarchitectures/comet lake | ||
+ | |successor=Alder Lake | ||
+ | |successor link=intel/microarchitectures/alder_lake | ||
+ | |contemporary=Tiger Lake | ||
+ | |contemporary link=intel/microarchitectures/tiger_lake | ||
}} | }} | ||
'''Rocket Lake''' ('''RKL''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices. | '''Rocket Lake''' ('''RKL''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices. |
Revision as of 05:18, 14 July 2020
Edit Values | |
Rocket Lake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Process | 14 nm |
Core Configs | 4 |
Pipeline | |
Type | Superscalar, Superpipeline |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Decode | 5-way |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX |
Cache | |
L1I Cache | 48 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L2 Cache | 512 KiB/core 4-way set associative |
L3 Cache | 2 MiB/core Up to 16-way set associative |
L4 Cache | 128 MiB/package on Iris Pro GPUs only |
Succession | |
Contemporary | |
Tiger Lake |
Rocket Lake (RKL) is a planned microarchitecture designed by Intel as a successor to Comet Lake for desktops and high-performance mobile devices.
Contents
Codenames
Core | Description | Graphics | Target |
---|---|---|---|
Rocket Lake S | Mainstream performance | GT2 | Desktop performance to value, AiOs, and minis |
Rocket Lake U | Ultra-low power | GT2 | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
Brands
Intel is expected to release Rocket Lake under 3 main brand families:
Logo | Family | General Description | Differentiating Features | |||||
---|---|---|---|---|---|---|---|---|
Cores | HT | AVX | AVX2 | TBT | ECC | |||
Core i3 | Low-end Performance | |||||||
Core i5 | Mid-range Performance | |||||||
Core i7 | High-end Performance |
Release Dates
Rocket Lake is expected to be released in Q4 2020 or Q1 2021.
Compatibility
This section is empty; you can help add the missing info by editing this page. |
Compiler support
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
ICC | -march=skylake |
-mtune=skylake
|
GCC | -march=skylake |
-mtune=skylake
|
LLVM | -march=skylake |
-mtune=skylake
|
Visual Studio | /arch:AVX2 |
/tune:skylake
|
CPUID
This section is empty; you can help add the missing info by editing this page. |
Architecture
Key changes from Coffee Lake
This section is empty; you can help add the missing info by editing this page. |
See also
- AMD Zen 2
Facts about "Rocket Lake - Microarchitectures - Intel"
codename | Rocket Lake + |
core count | 4 + |
designer | Intel + |
full page name | intel/microarchitectures/rocket lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Rocket Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |