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Difference between revisions of "cea-leti/microarchitectures/tsarlet"
< cea-leti

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{{cealeti title|TSARLET|arch}}
 
{{cealeti title|TSARLET|arch}}
−
{{microarchitecture}}
+
{{microarchitecture
 +
|atype=CPU
 +
|name=TSARLET
 +
|designer=CEA-Leti
 +
|manufacturer=STMicroelectronics
 +
|process=28 nm
 +
|process 2=65 nm
 +
|cores=96
 +
|type=Scalar
 +
|type 2=Single-issue
 +
|oooe=No
 +
|speculative=No
 +
|renaming=No
 +
|stages=5
 +
|decode=1-way
 +
|isa=MIPS32v1
 +
|l1i=16 KiB
 +
|l1i per=core
 +
|l1d=16 KiB
 +
|l1d per=core
 +
|l2=256 KiB
 +
|l2 per=core
 +
|l3=1 MiB
 +
|l3 per=core
 +
}}
 
'''TSARLET''' is a large-scale high-performance 3D stacked [[chiplets]]-based SoC technology demonstration by [[CEA-Leti]]. The project comprised 96 [[MIPS]] cores built using 6 [[chiplets]] [[3D stack]] on an active interposer in order to demonstarte in-package silicon [[scale-out]] capabilities with superior inter-chip capabilities while reducing the overall power and production cost.
 
'''TSARLET''' is a large-scale high-performance 3D stacked [[chiplets]]-based SoC technology demonstration by [[CEA-Leti]]. The project comprised 96 [[MIPS]] cores built using 6 [[chiplets]] [[3D stack]] on an active interposer in order to demonstarte in-package silicon [[scale-out]] capabilities with superior inter-chip capabilities while reducing the overall power and production cost.

Revision as of 01:13, 29 February 2020

Edit Values
TSARLET µarch
General Info
Arch TypeCPU
DesignerCEA-Leti
ManufacturerSTMicroelectronics
Process28 nm, 65 nm
Core Configs96
Pipeline
TypeScalar, Single-issue
OoOENo
SpeculativeNo
Reg RenamingNo
Stages5
Decode1-way
Instructions
ISAMIPS32v1
Cache
L1I Cache16 KiB/core
L1D Cache16 KiB/core
L2 Cache256 KiB/core
L3 Cache1 MiB/core

TSARLET is a large-scale high-performance 3D stacked chiplets-based SoC technology demonstration by CEA-Leti. The project comprised 96 MIPS cores built using 6 chiplets 3D stack on an active interposer in order to demonstarte in-package silicon scale-out capabilities with superior inter-chip capabilities while reducing the overall power and production cost.

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Facts about "TSARLET - Microarchitectures - CEA Leti"
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codenameTSARLET +
core count96 +
designerCEA-Leti +
full page namecea-leti/microarchitectures/tsarlet +
instance ofmicroarchitecture +
instruction set architectureMIPS32v1 +
manufacturerSTMicroelectronics +
microarchitecture typeCPU +
nameTSARLET +
pipeline stages5 +
process28 nm (0.028 μm, 2.8e-5 mm) + and 65 nm (0.065 μm, 6.5e-5 mm) +