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Revision as of 12:35, 27 February 2020

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Cascade Lake SP
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
IntroductionFebruary 24, 2020 (announced)
February 24, 2020 (launched)
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Word Size
8 octets
16 nibbles
64 bit
Process14 nm
0.014 μm
1.4e-5 mm
TechnologyCMOS
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Cascade Lake R (Cascade Lake Scalable Performance Refresh) is code name for Intel's series of server multiprocessors based on the Cascade Lake microarchitecture as part of the Purley platform serving as mid-cycle refresh to Cascade Lake SP. Cascade Lake R only targets mainstream entry and mid-range servers and therefore only support up to 2-way multiprocessing. As with Cascade Lake SP, these chips also support up to 28 cores, incorporate AVX512 x86 extension for neural network / deep learning workloads, and introduces persistent memory support. Cascade Lake R-based chips are manufactured on an enhanced 14 nm process and utilize the Lewisburg chipset.

Cascade Lake R-based models are branded as the 2nd-generation Xeon Bronze, Xeon Silver, and Xeon Gold processor families.

chipsetLewisburg +
designerIntel +
first announcedFebruary 24, 2020 +
first launchedFebruary 24, 2020 +
instance ofcore +
isax86-64 +
isa familyx86 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
microarchitectureCascade Lake +
nameCascade Lake SP +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket P + and LGA-3647 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +