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Difference between revisions of "cray/microarchitectures/rosetta"
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== Die == | == Die == | ||
| − | + | * TSMC [[16 nm process]] | |
| + | * 64 port | ||
| + | * 250 W | ||
| + | * tiled architecture | ||
| + | ** 32 tile blocks | ||
| + | ** peripheral function blocks | ||
| + | ''floorplan:'' | ||
| + | |||
| + | :[[File:cray rosetta die plot.jpg|600px]] | ||
== Bibliography == | == Bibliography == | ||
* {{bib|hoti|2019|Cray}} | * {{bib|hoti|2019|Cray}} | ||
Revision as of 22:10, 7 February 2020
| Edit Values | |
| Rosetta µarch | |
| General Info | |
| Arch Type | Switch |
| Designer | Cray |
| Manufacturer | TSMC |
| Introduction | 2019 |
| Process | 16 nm |
Rosetta is the microarchitecture for Cray's Slingshot ASIC Switch.
Process technology
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This section is empty; you can help add the missing info by editing this page. |
Overview
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This section is empty; you can help add the missing info by editing this page. |
Die
- TSMC 16 nm process
- 64 port
- 250 W
- tiled architecture
- 32 tile blocks
- peripheral function blocks
floorplan:
Bibliography
- Cray, 2019 IEEE Symposium on High-Performance Interconnects (HOTI).
Facts about "Rosetta - Microarchitectures - Cray"
| codename | Rosetta + |
| designer | Cray + |
| first launched | 2019 + |
| full page name | cray/microarchitectures/rosetta + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| name | Rosetta + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |