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Difference between revisions of "arm holdings/microarchitectures/mlp"
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{{armh title|Machine Learning Processor (MLP)|arch}} | {{armh title|Machine Learning Processor (MLP)|arch}} | ||
| − | {{microarchitecture}} | + | {{microarchitecture |
| + | |atype=NPU | ||
| + | |name=MLP | ||
| + | |designer=Arm Holdings | ||
| + | |manufacturer=TSMC | ||
| + | |manufacturer 2=Samsung | ||
| + | |manufacturer 3=UMC | ||
| + | |introduction=2019 | ||
| + | |process=16 nm | ||
| + | |process 2=7 nm | ||
| + | |processing elements=4 | ||
| + | |processing elements 2=8 | ||
| + | |processing elements 3=12 | ||
| + | |processing elements 4=16 | ||
| + | }} | ||
'''Machine Learning Processor''' ('''MLP''') is a first-generation [[neural processor]] microarchitecture designed by [[Arm]] for embedded and mobile SoCs. | '''Machine Learning Processor''' ('''MLP''') is a first-generation [[neural processor]] microarchitecture designed by [[Arm]] for embedded and mobile SoCs. | ||
Revision as of 01:30, 2 February 2020
| Edit Values | |
| MLP µarch | |
| General Info | |
| Arch Type | NPU |
| Designer | Arm Holdings |
| Manufacturer | TSMC, Samsung, UMC |
| Introduction | 2019 |
| Process | 16 nm, 7 nm |
| PE Configs | 4, 8, 12, 16 |
Machine Learning Processor (MLP) is a first-generation neural processor microarchitecture designed by Arm for embedded and mobile SoCs.
| codename | MLP + |
| designer | Arm Holdings + |
| first launched | 2019 + |
| full page name | arm holdings/microarchitectures/mlp + |
| instance of | microarchitecture + |
| manufacturer | TSMC +, Samsung + and UMC + |
| name | MLP + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |
| processing element count | 4 +, 8 +, 12 + and 16 + |