Difference between revisions of "annapurna labs/graviton/graviton"

	Edit Values
	AL73400
	General Info
Designer	Annapurna Labs
Manufacturer	TSMC
Model Number	AL73400
Part Number	AL73400-00-A0
Market	Server
Introduction	November 27, 2018 (announced); November 27, 2018 (launched)
	General Specs
Family	Alpine
Frequency	2,300 MHz
	Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A72
Core Name	Cortex-A72
Process	16 nm
Transistors	5,000,000,000
Technology	CMOS
Word Size	64 bit
Cores	16
Threads	16

Revision as of 10:15, 4 December 2019

Alpine AL73400, branded as AWS Graviton by Amazon, is a 16-core ARMv8 SoC designed by Annapurna Labs. The chip was first unveild by Peter DeSantis during Amazon's AWS re:Invent 2018. These processors are offered as part of Amazon's EC2 A1 instances. The AL73400 features 16 Cortex-A72 cores organized as four quad-core clusters, all operating at 2.3 GHz.

Cache

Main article: Cortex-A72 § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.25 MiB

1,280 KiB
1,310,720 B

L1I$	768 KiB 786,432 B 0.75 MiB	16x48 KiB
L1D$	512 KiB 524,288 B 0.5 MiB	16x32 KiB

L2$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		4x2 MiB

Raw info

lscpu

# lscpu

Architecture:          aarch64
Byte Order:            Little Endian
CPU(s):                16
On-line CPU(s) list:   0-15
Thread(s) per core:    1
Core(s) per socket:    4
Socket(s):             4
NUMA node(s):          1
Model:                 3
BogoMIPS:              166.66
L1d cache:             32K
L1i cache:             48K
L2 cache:              2048K
NUMA node0 CPU(s):     0-15
Flags:                 fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid

See ARMv8 features for a description of flags.

lstopo

# lstopo-no-graphics 

Machine (30GB)
  Package L#0 + L2 L#0 (2048KB)
    L1d L#0 (32KB) + L1i L#0 (48KB) + Core L#0 + PU L#0 (P#0)
    L1d L#1 (32KB) + L1i L#1 (48KB) + Core L#1 + PU L#1 (P#1)
    L1d L#2 (32KB) + L1i L#2 (48KB) + Core L#2 + PU L#2 (P#2)
    L1d L#3 (32KB) + L1i L#3 (48KB) + Core L#3 + PU L#3 (P#3)
  Package L#1 + L2 L#1 (2048KB)
    L1d L#4 (32KB) + L1i L#4 (48KB) + Core L#4 + PU L#4 (P#4)
    L1d L#5 (32KB) + L1i L#5 (48KB) + Core L#5 + PU L#5 (P#5)
    L1d L#6 (32KB) + L1i L#6 (48KB) + Core L#6 + PU L#6 (P#6)
    L1d L#7 (32KB) + L1i L#7 (48KB) + Core L#7 + PU L#7 (P#7)
  Package L#2 + L2 L#2 (2048KB)
    L1d L#8 (32KB) + L1i L#8 (48KB) + Core L#8 + PU L#8 (P#8)
    L1d L#9 (32KB) + L1i L#9 (48KB) + Core L#9 + PU L#9 (P#9)
    L1d L#10 (32KB) + L1i L#10 (48KB) + Core L#10 + PU L#10 (P#10)
    L1d L#11 (32KB) + L1i L#11 (48KB) + Core L#11 + PU L#11 (P#11)
  Package L#3 + L2 L#3 (2048KB)
    L1d L#12 (32KB) + L1i L#12 (48KB) + Core L#12 + PU L#12 (P#12)
    L1d L#13 (32KB) + L1i L#13 (48KB) + Core L#13 + PU L#13 (P#13)
    L1d L#14 (32KB) + L1i L#14 (48KB) + Core L#14 + PU L#14 (P#14)
    L1d L#15 (32KB) + L1i L#15 (48KB) + Core L#15 + PU L#15 (P#15)
  HostBridge L#0
    PCI 1d0f:8061
    PCI 1d0f:ec20
      Net L#0 "eth0"

cpuinfo

# cat /proc/cpuinfo

processor       : 0
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 1
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 2
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 3
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 4
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 5
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 6
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 7
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 8
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 9
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 10
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 11
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 12
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 13
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 14
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

processor       : 15
BogoMIPS        : 166.66
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x0
CPU part        : 0xd08
CPU revision    : 3

@@ Line 16: / Line 16: @@
 |microarch=Cortex-A72
 |core name=Cortex-A72
+|process=16 nm
+|transistors=5,000,000,000
 |technology=CMOS
 |word size=64 bit

base frequency	2,300 MHz (2.3 GHz, 2,300,000 kHz) +
core count	16 +
core name	Cortex-A72 +
designer	Annapurna Labs +
family	Alpine +
first announced	November 27, 2018 +
first launched	November 27, 2018 +
full page name	annapurna labs/graviton/graviton +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
l1$ size	1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ size	512 KiB (524,288 B, 0.5 MiB) +
l1i$ size	768 KiB (786,432 B, 0.75 MiB) +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldate	November 27, 2018 +
manufacturer	TSMC +
market segment	Server +
microarchitecture	Cortex-A72 +
model number	AL73400 +
name	AL73400 +
part number	AL73400-00-A0 +
process	16 nm (0.016 μm, 1.6e-5 mm) +
technology	CMOS +
thread count	16 +
transistor count	5,000,000,000 +
word size	64 bit (8 octets, 16 nibbles) +

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