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Difference between revisions of "intel/microarchitectures/tremont"
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(Added XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB and ENCLV) |
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|extension 11=PCLMUL | |extension 11=PCLMUL | ||
|extension 12=RDRND | |extension 12=RDRND | ||
| − | |extension 13=SHA | + | |extension 13=XSAVE |
| + | |extension 14=XSAVEOPT | ||
| + | |extension 15=FSGSBASE | ||
| + | |extension 16=PTWRITE | ||
| + | |extension 17=RDPID | ||
| + | |extension 18=SGX | ||
| + | |extension 19=UMIP | ||
| + | |extension 20=GFNI-SSE | ||
| + | |extension 21=CLWB | ||
| + | |extension 22=ENCLV | ||
| + | |extension 23=SHA | ||
|core name=Elkhart Lake | |core name=Elkhart Lake | ||
|core name 2=Skyhawk Lake | |core name 2=Skyhawk Lake | ||
Revision as of 18:05, 15 July 2019
| Edit Values | |
| Tremont µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019/2020 |
| Process | 10 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, ENCLV, SHA |
| Cores | |
| Core Names | Elkhart Lake, Skyhawk Lake |
| Succession | |
Tremont is Intel's successor to Goldmont Plus, a 10 nm microarchitecture for ultra-low power devices and microservers.
Contents
Codenames
| Platform | Core Name | PCH |
|---|---|---|
| Skyhawk Lake | ||
| Jacobsville | Elkhart Lake | Mule Creek Canyon |
Brands
 |
This section is empty; you can help add the missing info by editing this page. |
Release Dates
| |
This section is empty; you can help add the missing info by editing this page. |
Technology
Tremont appear to be planned for Intel's 10 nm process.
Compiler support
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| ICC | -march=tremont |
-mtune=tremont
|
| GCC | -march=tremont |
-mtune=tremont
|
| LLVM | -march=tremont |
-mtune=tremont
|
| Visual Studio | /arch:? |
/tune:?
|
CPUID
| Core | Extended Family |
Family | Extended Model |
Model |
|---|---|---|---|---|
| ? | 0 | 0x6 | 0x8 | 0x6 |
| Family 6 Model 134 | ||||
Architecture
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Key changes from Goldmont Plus
- Graphics
New instructions
Tremont introduced a number of new instructions:
-
CLWB- Force cache line write-back without flush -
ENCLV- SGX oversubscription instructions -
CLDEMOTE- Cache line demote instruction -
SSE_GFNI- SSE-based Galois Field New Instructions - Direct store instructions: MOVDIRI, MOVDIR64B
- User wait instructions: TPAUSE, UMONITOR, UMWAIT
- Split Lock Detection - detection and cause an exception for split locks
Facts about "Tremont - Microarchitectures - Intel"
| codename | Tremont + |
| designer | Intel + |
| full page name | intel/microarchitectures/tremont + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tremont + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |