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(A6-9920C)
 
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'''A6-9920C''' is a {{arch|64}} [[dual-core]] ultra-low power [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Excavator|Excavator microarchitecture|l=arch}} and is fabricated on a [[28 nm process]]. The A6-9920C operates at a base frequency of 1.8 GHz with a [[TDP]] of 6 W and a {{amd|Turbo Core|turbo}} frequency of 2.7 GHz. This APU supports single-channel DDR4-1866 memory and incorporates {{amd|Radeon R5 series}} graphics operating at up to 720 MHz.
 
'''A6-9920C''' is a {{arch|64}} [[dual-core]] ultra-low power [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Excavator|Excavator microarchitecture|l=arch}} and is fabricated on a [[28 nm process]]. The A6-9920C operates at a base frequency of 1.8 GHz with a [[TDP]] of 6 W and a {{amd|Turbo Core|turbo}} frequency of 2.7 GHz. This APU supports single-channel DDR4-1866 memory and incorporates {{amd|Radeon R5 series}} graphics operating at up to 720 MHz.
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== Cache ==
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{{main|amd/microarchitectures/excavator#Memory_Hierarchy|l1=Excavator § Cache}}
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{{cache size
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|l1 cache=160 KiB
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|l1i cache=96 KiB
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|l1i break=1x96 KiB
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|l1d cache=64 KiB
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|l1d break=2x32 KiB
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|l2 cache=1 MiB
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|l2 break=2x1 MiB
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR4-1866
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|ecc=No
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|controllers=1
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|channels=1
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|max bandwidth=13.91 GiB/s
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|bandwidth schan=13.91 GiB/s
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}}
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== Expansions ==
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{{expansions main
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|
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{{expansions entry
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|type=PCIe
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|pcie revision=3.0
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|pcie lanes=8
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|pcie config=1x8
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}}
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}}

Revision as of 17:51, 7 January 2019

Edit Values
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General Info
Microarchitecture

A6-9920C is a 64-bit dual-core ultra-low power x86 mobile microprocessor introduced by AMD in early 2019. This processor is based on AMD's Excavator microarchitecture and is fabricated on a 28 nm process. The A6-9920C operates at a base frequency of 1.8 GHz with a TDP of 6 W and a turbo frequency of 2.7 GHz. This APU supports single-channel DDR4-1866 memory and incorporates Radeon R5 series graphics operating at up to 720 MHz.

Cache

Main article: Excavator § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$160 KiB
163,840 B
0.156 MiB
L1I$96 KiB
98,304 B
0.0938 MiB
1x96 KiB  
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  2x1 MiB  

Memory controller

[Edit/Modify Memory Info]

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Integrated Memory Controller
Max TypeDDR4-1866
Supports ECCNo
Controllers1
Channels1
Max Bandwidth13.91 GiB/s
14,243.84 MiB/s
14.936 GB/s
14,935.749 MB/s
0.0136 TiB/s
0.0149 TB/s
Bandwidth
Single 13.91 GiB/s

Expansions

[Edit/Modify Expansions Info]

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Expansion Options
PCIeRevision: 3.0
Max Lanes: 8
Configuration: 1x8
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Facts about "A6-9220C - AMD"
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A6-9220C - AMD#pcie +
full page nameamd/a6/a6-9220c +
has ecc memory supportfalse +
instance ofmicroprocessor +
l1$ size160 KiB (163,840 B, 0.156 MiB) +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ size96 KiB (98,304 B, 0.0938 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate1900 +
max memory bandwidth13.91 GiB/s (14,243.84 MiB/s, 14.936 GB/s, 14,935.749 MB/s, 0.0136 TiB/s, 0.0149 TB/s) +
max memory channels1 +
supported memory typeDDR4-1866 +