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From WikiChip
Difference between revisions of "arm holdings/microarchitectures/poseidon"
(Poseidon) |
(No difference)
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Revision as of 01:17, 14 December 2018
| Edit Values | |
| Ares µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Succession | |
Poseidon is the successor to Zeus, a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
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Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/poseidon&oldid=84911"
Facts about "Poseidon - Microarchitectures - ARM"
| codename | Ares + |
| designer | ARM Holdings + |
| full page name | arm holdings/microarchitectures/poseidon + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Ares + |