Semiconductor & Computer Engineering
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| successor link = amd/microarchitectures/k10 | | successor link = amd/microarchitectures/k10 | ||
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| − | '''K9''' was a planned [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|K8}}. AMD intended to bring massive parallelism | + | '''K9''' was a planned [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|K8}}. The K9 codename might cover multiple projects at AMD. A deep pipeline design led by Mitch Alsup as Chief Architect, another one intended to bring massive parallelism<ref>Anand Lal Shimpi, [https://www.anandtech.com/show/2229/5 Why is Barcelona late? - AMD - The Road Ahead], anandtech.com. Retrieved on December 1, 2018</ref> and finally, using K9 as a codename for dual-core {{\\|K8}}. |
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| + | The whole set of intended features and the exact reasons AMD cancelled K9 remain unknown. | ||
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| + | == Deep pipeline design == | ||
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| + | The design was led by Mitch Alsup as Chief Architect and attempted to directly compete with [[Intel]] [[netburst|NetBurst]]. It featured a deep pipeline and an advanced trace cache. | ||
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| + | According to Alsup, it was designed to be close to 95% of original {{\\|K8}} IPC but reach 5GHz frequency in a 35 nm process. At the time of cancellation most of the logic was running in SPICE at 5GHz and majority of the layout was done. | ||
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| + | The K9 pipeline was dual-quad issue. It was described by Alsup as: "K9 fetched 8 instructions every other cycle and made 2 branch predictions associated with 3 next fetch addresses every other cycle. K9 issued 4 instructions per cycle and took 2 cycles to issue a fetch width." | ||
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| + | Reportedly, the design was cancelled due to leakage current problems amplified by necessity to embrace the multi-core era. K9's DDR2 SDRAM controller was later used in {{\\|K8}} Rev F and its northbridge technology got put in {{\\|K8}} Rev G. | ||
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| + | == References == | ||
Latest revision as of 16:28, 1 December 2018
| Edit Values | |
| K9 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | AMD |
| Process | 65 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
K9 was a planned microarchitecture developed by AMD as a successor to K8. The K9 codename might cover multiple projects at AMD. A deep pipeline design led by Mitch Alsup as Chief Architect, another one intended to bring massive parallelism[1] and finally, using K9 as a codename for dual-core K8.
The whole set of intended features and the exact reasons AMD cancelled K9 remain unknown.
Deep pipeline design[edit]
The design was led by Mitch Alsup as Chief Architect and attempted to directly compete with Intel NetBurst. It featured a deep pipeline and an advanced trace cache.
According to Alsup, it was designed to be close to 95% of original K8 IPC but reach 5GHz frequency in a 35 nm process. At the time of cancellation most of the logic was running in SPICE at 5GHz and majority of the layout was done.
The K9 pipeline was dual-quad issue. It was described by Alsup as: "K9 fetched 8 instructions every other cycle and made 2 branch predictions associated with 3 next fetch addresses every other cycle. K9 issued 4 instructions per cycle and took 2 cycles to issue a fetch width."
Reportedly, the design was cancelled due to leakage current problems amplified by necessity to embrace the multi-core era. K9's DDR2 SDRAM controller was later used in K8 Rev F and its northbridge technology got put in K8 Rev G.
References[edit]
- ↑ Anand Lal Shimpi, Why is Barcelona late? - AMD - The Road Ahead, anandtech.com. Retrieved on December 1, 2018
| codename | K9 + |
| designer | AMD + |
| full page name | amd/microarchitectures/k9 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | AMD + |
| microarchitecture type | CPU + |
| name | K9 + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + |