Semiconductor & Computer Engineering
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Both of the new instructions must follow by a <code>SFENCE</code> to ensure all flushes are completed before continuing. | Both of the new instructions must follow by a <code>SFENCE</code> to ensure all flushes are completed before continuing. | ||
| + | |||
| + | == Microarchitecture support == | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! rowspan="2" | Instruction !! colspan="2" | Introduction | ||
| + | |- | ||
| + | ! [[Intel]] !! [[AMD]] | ||
| + | |- | ||
| + | | <code>CLFLUSHOPT</code> || {{intel|Skylake (server)|l=arch}}<br>{{intel|Skylake (client)|l=arch}}<br>{{intel|Goldmont|l=arch}} | ||
| + | |- | ||
| + | | <code>CLWB</code> || {{intel|Skylake (server)|l=arch}}<br>{{intel|Ice Lake (client)|l=arch}} || {{amd|Zen 2|l=arch}} | ||
| + | |} | ||
Revision as of 11:24, 19 November 2018
Instruction Set Architecture
- Instructions
- Addressing Modes
- Registers
- Model-Specific Register
- Assembly
- Interrupts
- Micro-Ops
- Timer
- Calling Convention
- Microarchitectures
- CPUID
Persistent memory extensions are a set of x86 instructions designed to improve the usability of working with storage-class memory.
Overview
Intel adopted the SNIA NVM Programming Model for working with persistent memory. This model allows for direct access (DAX) using byte-addressable operations (i.e., load/store), however, the persistence of the data in the cache is not guaranteed until it has entered the persistence domain. x86 provides a set of instructions for flushing cache lines in a more optimized way. In addition to existing x86 instructions such as non-temporal stores, CLFLUSH, and WBINVD (kernel only), two new instructions were added:
| Instruction | Description |
|---|---|
CLFLUSHOPT |
Optimized CLFLUSH; Behaves similarly to CLFLUSH but without the serialization, thereby optimized for performance by allowing for some concurrency when executing multiple CLFLUSHOPT instructions back-to-back.
|
CLWB |
Cache line write back; behaves similarly to CLFLUSHOPT but keeps the cache line valid (i.e., the cache line is flushed and then marked as no longer dirty) thereby optimized for performance by keeping the line in the cache, increasing the cache of a cache hit.
|
Both of the new instructions must follow by a SFENCE to ensure all flushes are completed before continuing.
Microarchitecture support
| Instruction | Introduction | |
|---|---|---|
| Intel | AMD | |
CLFLUSHOPT |
Skylake (server) Skylake (client) Goldmont | |
CLWB |
Skylake (server) Ice Lake (client) |
Zen 2 |