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{{arm title|AArch64}}{{arm isa main}} | {{arm title|AArch64}}{{arm isa main}} | ||
'''AArch64''' is the {{arch|64}} execution state of the {{\\|ARMv8}} ISA. A machine in this state executes operates on the {{\\|A64}} instruction set. This is in contrast to the {{\\|AArch32}} which describes the classical 32-bit ARM execution state. | '''AArch64''' is the {{arch|64}} execution state of the {{\\|ARMv8}} ISA. A machine in this state executes operates on the {{\\|A64}} instruction set. This is in contrast to the {{\\|AArch32}} which describes the classical 32-bit ARM execution state. | ||
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| + | == Overview == | ||
| + | The AArch64 execution state was introduced with the {{\\|ARMv8}} ISA for machines executing {{\\|A64}} instructions. A machine in AArch64 can only execute A64 instructions and cannot execute {{\\|A32}} or {{\\|T32}} instructions. However, unlike in {{\\|AArch32}}, in the 64-bit state, instructions can access both the 64-bit and 32-bit registers. | ||
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Revision as of 12:21, 20 September 2018
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AArch64 is the 64-bit execution state of the ARMv8 ISA. A machine in this state executes operates on the A64 instruction set. This is in contrast to the AArch32 which describes the classical 32-bit ARM execution state.
Overview
The AArch64 execution state was introduced with the ARMv8 ISA for machines executing A64 instructions. A machine in AArch64 can only execute A64 instructions and cannot execute A32 or T32 instructions. However, unlike in AArch32, in the 64-bit state, instructions can access both the 64-bit and 32-bit registers.
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