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Difference between revisions of "intel/microarchitectures/tremont"
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Revision as of 17:48, 10 September 2018
| Edit Values | |
| Tremont µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2018/2019 |
| Process | 10 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
| Cores | |
| Core Names | Gemini Lake |
| Succession | |
Tremont is Intel's successor to Goldmont Plus, a 10 nm microarchitecture for ultra-low power devices and microservers.
Contents
Codenames
| Platform | Core Name |
|---|---|
| Jacobsville | Elkhart Lake? |
Brands
 |
This section is empty; you can help add the missing info by editing this page. |
Release Dates
| |
This section is empty; you can help add the missing info by editing this page. |
Technology
Tremont appear to be planned for Intel's 10 nm process.
Compiler support
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| ICC | -march=? |
-mtune=?
|
| GCC | -march=? |
-mtune=?
|
| LLVM | -march=? |
-mtune=?
|
| Visual Studio | /arch:? |
/tune:?
|
CPUID
| Core | Extended Family |
Family | Extended Model |
Model |
|---|---|---|---|---|
| ? | 0 | 0x6 | 0x8 | 0x6 |
| Family 6 Model 134 | ||||
Architecture
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Key changes from Goldmont Plus
- 10 nm process (From 14 nm)
This list is incomplete; you can help by expanding it.
New instructions
Termont introduced a number of new instructions:
-
CLWB- Force cache line write-back without flush -
ENCLV- SGX oversubscription instructions -
CLDEMOTE- Cache line demote instruction -
SSE_GFNI- SSE-based Galois Field New Instructions - Direct store instructions: MOVDIRI, MOVDIR64B
- User wait instructions: TPAUSE, UMONITOR, UMWAIT
- Split Lock Detection - detection and cause an exception for split locks
Facts about "Tremont - Microarchitectures - Intel"
| codename | Tremont + |
| designer | Intel + |
| full page name | intel/microarchitectures/tremont + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Tremont + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |