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    Difference between revisions of "arm holdings/microarchitectures/neoverse n1"    
                	
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| − | '''Ares''' is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. Ares appears to be a derivative of the {{  | + | '''Ares''' is a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. Ares appears to be a derivative of the {{armh|Cortex-A76|l=arch}} designed for higher TDP and performance.  | 
{{future information}}  | {{future information}}  | ||
Revision as of 16:49, 8 September 2018
| Edit Values | |
| Cortex-Ares µarch | |
| General Info | |
| Arch Type | CPU | 
| Designer | ARM Holdings | 
| Manufacturer | TSMC | 
| Process | 10 nm, 7 nm | 
| Pipeline | |
| OoOE | Yes | 
| Speculative | Yes | 
| Reg Renaming | Yes | 
Ares is a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. Ares appears to be a derivative of the Cortex-A76 designed for higher TDP and performance.
Facts about "Neoverse N1 - Microarchitectures - ARM"
| codename | Cortex-Ares + | 
| designer | ARM Holdings + | 
| full page name | arm holdings/microarchitectures/neoverse n1 + | 
| instance of | microarchitecture + | 
| manufacturer | TSMC + | 
| microarchitecture type | CPU + | 
| name | Cortex-Ares + | 
| process | 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |