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<tr><th>Processors</th><td>5,184<br>2 x 72 x 36</td><td>&nbsp;</td><th>Type</th><td>[[DDR4]]</td><td>[[NVMe]]</td></tr>
 
<tr><th>Processors</th><td>5,184<br>2 x 72 x 36</td><td>&nbsp;</td><th>Type</th><td>[[DDR4]]</td><td>[[NVMe]]</td></tr>
 
<tr><th>Racks</th><td>36</td><td>&nbsp;</td><th>Node</th><td>128 GiB</td><td>?</td></tr>
 
<tr><th>Racks</th><td>36</td><td>&nbsp;</td><th>Node</th><td>128 GiB</td><td>?</td></tr>
<tr><th>Peak FLOPS</th><td>2.322 petaFLOPS</td><td>&nbsp;</td><th>Astra</th><td>324 TiB</td><td>403 TB</td></tr>
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<tr><th>Peak FLOPS</th><td>2.322 petaFLOPS (SP)<br>1.161 petaFLOPS (DP)</td><td>&nbsp;</td><th>Astra</th><td>324 TiB</td><td>403 TB</td></tr>
 
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Revision as of 20:46, 23 August 2018

Astra Illustration

Astra is a petascale ARM supercomputer designed for Sandia National Laboratories expeced to be deployed in mid-2018. This is the first ARM-based supercomputer to exceed 1 petaFLOPS.

History

Roadmap to Astra

Astra is an ARM-based supercomputer expected to be deployed at Sandia National Laboratories. The computer is one of a series of prototypes commissioned by the U.S. Department of Energy as part of a program that evaluates the feasibility of emerging high-performance computing architectures as production platforms to support NNSA's mission. Specifically, Astra is designed to demonstrate the viability of ARM for DOE NNSA Supercomputing. Astra is the fourth prototype as part of the Vanguard project initiative and is by far the largest ARM-based supercomputer designed to that point.

Overview

Astra is the first ARM-based petascale supercomputer. The system consists of 5,184 Cavium ThunderX2 CN9975 processors with slightly over 1.2 MW power consumption for a peak performance of 2.322 petaFLOPS. Each ThunderX2 CN9975 has 28 cores operating at 2 GHz. Astra has close around 700 terabytes of memory and uses a 3-level fat tree interconnect.

Components Total Memory
Processors5,184
2 x 72 x 36
 TypeDDR4NVMe
Racks36 Node128 GiB?
Peak FLOPS2.322 petaFLOPS (SP)
1.161 petaFLOPS (DP)
 Astra324 TiB403 TB

Architecture

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System

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Compute Rack

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Compute Node

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Socket

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Full-node

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Bibliography