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Difference between revisions of "intel/microarchitectures/polaris"
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{{intel title|Polaris|arch}}
 
{{intel title|Polaris|arch}}
−
{{microarchitecture}}
+
{{microarchitecture
 +
|atype=CPU
 +
|name=Polaris
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|introduction=February 2007
 +
|process=65 nm
 +
|cores=80
 +
|type=VLIW
 +
|stages=9
 +
|l1i=3 KiB
 +
|l1i per=core
 +
|l1d=2 KiB
 +
|l1d per=core
 +
|predecessor=Larrabee
 +
|predecessor link=intel/microarchitectures/larrabee
 +
}}
 
'''Polaris''' was a research [[microarchitecture]] designed by [[Intel]] [[Intel Labs|Labs]] demonstarting the theoretical capabilities of a [[many-core]] chip performing 1 [[trillion floating point operations]].
 
'''Polaris''' was a research [[microarchitecture]] designed by [[Intel]] [[Intel Labs|Labs]] demonstarting the theoretical capabilities of a [[many-core]] chip performing 1 [[trillion floating point operations]].

Revision as of 18:54, 8 April 2018

Edit Values
Polaris µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionFebruary 2007
Process65 nm
Core Configs80
Pipeline
TypeVLIW
Stages9
Cache
L1I Cache3 KiB/core
L1D Cache2 KiB/core
Succession

Polaris was a research microarchitecture designed by Intel Labs demonstarting the theoretical capabilities of a many-core chip performing 1 trillion floating point operations.

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Facts about "Polaris - Microarchitectures - Intel"
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codenamePolaris +
core count80 +
designerIntel +
first launchedFebruary 2007 +
full page nameintel/microarchitectures/polaris +
instance ofmicroarchitecture +
manufacturerIntel +
microarchitecture typeCPU +
namePolaris +
pipeline stages9 +
process65 nm (0.065 μm, 6.5e-5 mm) +