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Difference between revisions of "intel/microarchitectures/tremont"
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* {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush | * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush | ||
+ | * {{x86|ENCLV|<code>ENCLV</code>}} - SGX oversubscription instructions | ||
+ | * {{x86|CLDEMOTE|<code>CLDEMOTE</code>}} - Cache line demote instruction | ||
+ | * Direct store instructions: MOVDIRI, MOVDIR64B | ||
+ | * User wait instructions: TPAUSE, UMONITOR, UMWAIT | ||
+ | * Split Lock Detection |
Revision as of 14:10, 4 April 2018
Edit Values | |
Tremont µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | 2018/2019 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA |
Cores | |
Core Names | Gemini Lake |
Succession | |
Contents
Codenames
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Brands
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Release Dates
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Technology
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Architecture
Key changes from Goldmont Plus
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New instructions
Termont introduced a number of new instructions:
Facts about "Tremont - Microarchitectures - Intel"
codename | Tremont + |
designer | Intel + |
full page name | intel/microarchitectures/tremont + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Tremont + |