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Difference between revisions of "intel/microarchitectures/cascade lake"
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* Support for DDR-T / Optane DIMMs | * Support for DDR-T / Optane DIMMs | ||
* Architectural improvements | * Architectural improvements | ||
| + | * Security | ||
| + | ** Fix for {{cve|CVE-2017-5715}} (Spectre, Variant 2) | ||
| + | ** Fix for {{cve|CVE-2017-5754}} (Meltdown, Variant 3) | ||
{{expand list}} | {{expand list}} | ||
====New instructions ==== | ====New instructions ==== | ||
Revision as of 17:25, 15 March 2018
| Edit Values | |
| Cascade Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2018 |
| Process | 14 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 14-19 |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512 |
| Cache | |
| L1I Cache | 32 KiB/core 8-way set associative |
| L1D Cache | 32 KiB/core 8-way set associative |
| L2 Cache | 1 MiB/core 16-way set associative |
| L3 Cache | 1.375 MiB/core 11-way set associative |
| Cores | |
| Core Names | Cascade Lake X, Cascade Lake SP |
| Succession | |
| Contemporary | |
| Coffee Lake | |
Cascade Lake (CLX) is Intel's successor to Skylake, an enhanced 14nm+ process microarchitecture for enthusiasts and servers. Cascade Lake is the "Optimization" phase as part of Intel's PAO model.
For desktop enthusiasts, Skylake is branded Core i7, and Core i9 processors (under the Core X series). For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.
Contents
Codenames
| Core | Target |
|---|---|
| Cascade Lake X | High-end desktops & enthusiasts market |
| Cascade Lake W | Enterprise/Business workstations |
| Cascade Lake SP | Server Scalable Processors |
Brands
 |
This section is empty; you can help add the missing info by editing this page. |
Release Dates
Cascade Lake is expected to be released in mid-2018.
Process Technology
| |
This section is empty; you can help add the missing info by editing this page. |
Architecture
As with Skylake, Cascade Lake is also based on the Purley platform and is designed as a drop-in upgrade.
Key changes from Skylake
- Supports higher DDR4 data rates
- Support for DDR-T / Optane DIMMs
- Architectural improvements
- Security
- Fix for CVE-2017-5715 (Spectre, Variant 2)
- Fix for CVE-2017-5754 (Meltdown, Variant 3)
This list is incomplete; you can help by expanding it.
New instructions
Cascade Lake introduced a number of new instructions:
-
AVX-512 VNNI- AVX-512 Vector Neural Network Instructions
Block Diagram
| |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Cascade Lake - Microarchitectures - Intel"
| codename | Cascade Lake + |
| designer | Intel + |
| first launched | 2018 + |
| full page name | intel/microarchitectures/cascade lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Cascade Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |