From WikiChip
Difference between revisions of "amd/ryzen 7/2700"
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+ | == Cache == | ||
+ | {{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=768 KiB | ||
+ | |l1i cache=512 KiB | ||
+ | |l1i break=8x64 KiB | ||
+ | |l1i desc=4-way set associative | ||
+ | |l1d cache=256 KiB | ||
+ | |l1d break=8x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=4 MiB | ||
+ | |l2 break=8x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=16 MiB | ||
+ | |l3 break=2x8 MiB | ||
+ | |l3 desc=16-way set associative | ||
+ | }} |
Revision as of 06:48, 7 March 2018
Edit Values | |
Ryzen 7 2700 | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 2700 |
Market | Desktop |
Introduction | March, 2018 (announced) April 19, 2018 (launched) |
Release Price | $299 |
Shop | Amazon |
General Specs | |
Family | Ryzen 7 |
Series | 2000 |
Locked | No |
Frequency | 3,200 MHz |
Turbo Frequency | 4,100 MHz (1 core) |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 32 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen+ |
Chipset | Promontory |
Core Name | Pinnacle Ridge |
Process | 12 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 64 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 65 W |
Packaging | |
Template:packages/amd/socket am4 |
Ryzen 7 2700 is a 64-bit octa-core high-end performance x86 desktop microprocessor set to be introduced by AMD in early 2018. This processor is based on AMD's Zen+ microarchitecture and is fabricated on a 12 nm process. The 2700 operates at a base frequency of 3.2 GHz with a TDP of 65 W and a Boost frequency of up to 4.1 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2933 memory.
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Ryzen 7 2700 - AMD"
base frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
chipset | Promontory + |
clock multiplier | 32 + |
core count | 8 + |
core name | Pinnacle Ridge + |
designer | AMD + |
family | Ryzen 7 + |
first announced | March 2018 + |
first launched | April 19, 2018 + |
full page name | amd/ryzen 7/2700 + |
has locked clock multiplier | false + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
ldate | 3000 + |
manufacturer | GlobalFoundries + |
market segment | Desktop + |
max cpu count | 1 + |
max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
microarchitecture | Zen+ + |
model number | 2700 + |
name | Ryzen 7 2700 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
release price | $ 299.00 (€ 269.10, £ 242.19, ¥ 30,895.67) + |
series | 2000 + |
smp max ways | 1 + |
tdp | 65 W (65,000 mW, 0.0872 hp, 0.065 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 4,100 MHz (4.1 GHz, 4,100,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |