Revision as of 16:14, 13 December 2017

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Atom C3955
General Info
Designer	Intel
Manufacturer	Intel
Model Number	C3955
Part Number	HW8076503528301
S-Spec	SR3F3
Market	Server, Embedded
Introduction	August 15, 2017 (announced) August 15, 2017 (launched)
Release Price	$434.00
Shop	Amazon
General Specs
Family	Atom
Series	3000
Locked	Yes
Frequency	2,100 MHz
Turbo Frequency	2,400 MHz (1 core)
Clock multiplier	21
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Goldmont
Core Name	Denverton
Core Family	6
Core Model	95
Core Stepping	B1
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	16
Threads	16
Max Memory	256 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	32 W
Tjunction	0 °C – 100 °C
Tcase	0 °C – 78 °C
Tstorage	-25 °C – 125 °C
Packaging
Package FCBGA-1310 (BGA) Dimension 34 mm x 28 mm Ball Count 1310 Ball Comp SAC405 Interconnect BGA-1310

Atom C3955 is a 64-bit hexadeca-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3955, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2.1 GHz with a TDP of 32 W and a turbo boost frequency of up to 2.4 GHz. The C3955 supports up to 256 GiB of dual-channel DDR4-2400 ECC memory. This model is part of Denverton's Server and Cloud Storage SKUs.

Cache

Main article: Goldmont § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 896 KiB 917,504 B 0.875 MiB L1I$ 512 KiB 524,288 B 0.5 MiB 16x32 KiB 8-way set associative write-back L1D$ 384 KiB 393,216 B 0.375 MiB 16x24 KiB 6-way set associative write-back L2$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     8x2 MiB 16-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3L-1600, DDR4-2400 Supports ECC Yes Max Mem 256 GiB Controllers 1 Channels 2 Max Bandwidth 35.76 GiB/s 36,618.24 MiB/s 38.397 GB/s 38,397.008 MB/s 0.0349 TiB/s 0.0384 TB/s Bandwidth Single 17.88 GiB/s Double 35.76 GiB/s

Expansions

This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 20 Configuration: x8, x4, x2 USB Revision: 3.0 Max Ports: 8 HSIO Max Lanes: 20

Networking

[Edit/Modify Network Info]

	Networking
	Ethernet 10GbE Yes (Ports: 4)

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) MPX Memory Protection Extensions