Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "cavium/octeon plus/cn5750-800bg1217-ssp"
m (Bot: corrected param) |
m (Bot: moving all {{mpu}} to {{chip}}) |
||
| Line 1: | Line 1: | ||
{{cavium title|CN5750-800 SSP}} | {{cavium title|CN5750-800 SSP}} | ||
| − | {{ | + | {{chip |
| name = Cavium CN5750-800 SSP | | name = Cavium CN5750-800 SSP | ||
| no image = | | no image = | ||
Latest revision as of 15:12, 13 December 2017
| Edit Values | |||||||||
| Cavium CN5750-800 SSP | |||||||||
 | |||||||||
| General Info | |||||||||
| Designer | Cavium | ||||||||
| Manufacturer | TSMC | ||||||||
| Model Number | CN5750-800 SSP | ||||||||
| Part Number | CN5750-800BG1217-SSP | ||||||||
| Market | Storage | ||||||||
| Introduction | Jun 26, 2007 (announced) August, 2007 (launched) | ||||||||
| General Specs | |||||||||
| Family | OCTEON Plus | ||||||||
| Series | CN57xx | ||||||||
| Frequency | 800 MHz | ||||||||
| Microarchitecture | |||||||||
| ISA | MIPS64 (MIPS) | ||||||||
| Microarchitecture | cnMIPS | ||||||||
| Process | 90 nm | ||||||||
| Technology | CMOS | ||||||||
| Word Size | 64 bit | ||||||||
| Cores | 12 | ||||||||
| Threads | 12 | ||||||||
| Multiprocessing | |||||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||||
| Packaging | |||||||||
| |||||||||
CN5750-800 SSP is a 64-bit dodeca-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
|||||||||||||||||||||||||
Memory controller[edit]
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
Expansions[edit]
 |
Expansion Options
|
|||||||||||
|
||||||||||||
Networking[edit]
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
 |
Networking
|
|||||
|
||||||
Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
 |
Hardware Accelerators
|
|||||||||||||||||||||||
|
||||||||||||||||||||||||
Block diagram[edit]
Datasheet[edit]
Facts about "CN5750-800 SSP - Cavium"
