From WikiChip
Difference between revisions of "amd/duron/dhd1100amt1b"
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Revision as of 14:21, 13 December 2017
Edit Values | |
Duron 1100 | |
General Info | |
Designer | AMD |
Manufacturer | AMD |
Model Number | Duron 1100 |
Part Number | DHD1100AMT1B |
Market | Desktop |
Introduction | October 1, 2001 (announced) October 1, 2001 (launched) |
Shop | Amazon |
General Specs | |
Family | Duron |
Series | Duron Desktop |
Locked | Yes |
Frequency | 1100 MHz |
Bus type | FSB |
Bus speed | 100 MHz |
Bus rate | 200 MT/s |
Clock multiplier | 11 |
CPUID | 670 |
Microarchitecture | |
Microarchitecture | K7 |
Core Name | Morgan |
Core Family | 6 |
Core Model | 7 |
Core Stepping | 0 |
Process | 180 nm |
Transistors | 25,180,000 |
Technology | CMOS |
Die | 105.68 mm² |
Word Size | 32 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 4 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 1.75 V ± 0.15 V |
TDP | 50.3 W |
Tcase | 0 °C – 90 °C |
Tstorage | -40 °C – 100 °C |
The Duron 11000 based on the Morgan core was a 32-bit x86 microprocessor developed by AMD and introduced in late 2001. This model was part of the second generation of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 1100 MHz with a bus capable of 200 MT/s with a max TDP of 50.3 W and a typical TDP of 46.2 W.
Cache
- Main article: K7 § Cache
Cache Info [Edit Values] | ||
L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
L2$ | 64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB |
1x64 KiB 16-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Halt State
- Sleep State
Documents
DataSheet
- AMD Duron Processor Model 7 Data Sheet; Publication # 24310; Rev: G; Issue Date: January 2002.
Other
- AMD Duron Processor Model 7 Revision Guide; Publication # 24806; Rev: E; Issue Date: October 2003.
See also
Facts about "Duron 1100 (Morgan) - AMD"
has feature | Halt State + and Sleep State + |
l1d$ description | 2-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |