Semiconductor & Computer Engineering
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RISC-V defines a set of '''registers''' that are part of the core ISA. | RISC-V defines a set of '''registers''' that are part of the core ISA. | ||
Revision as of 01:44, 12 December 2017
Instruction Set Architecture
- Foundation
- Non-Standard Extensions
- Addressing Modes
- Registers
- Assembly
- Interrupts
- Microarchitectures
RISC-V defines a set of registers that are part of the core ISA.
Overview
RISC-V base ISA consists of 32 general-purpose registers x1-x31 which hold integer values. The register x0 is hardwired to the constant 0. There is an additional user-visible program counter pc register which holds the address of the current instruction. RISC-V does not define a specific subroutine return address link register, but it does suggest that the standard software calling convention should use register x1 to store the return address on a call.
The width of those registers are defined by the RISC-V base variant used. That is, for RV32, the registers are 32 bits wide, for RV64, they are 64 bits, and for RV128, those registers are 128 bit wide.
Note that RISC-V defines a special ISA E for resource-constrained embedded applications which only defines 16 registers.
