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Difference between revisions of "intel/celeron/j4105"
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== Cache ==
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{{main|intel/microarchitectures/goldmont_plus#Memory_Hierarchy|l1=Goldmont Plus § Cache}}
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{{cache size
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|l1 cache=256 KiB
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|l1i cache=128 KiB
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|l1i break=4x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=96 KiB
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|l1d break=4x24 KiB
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|l1d desc=6-way set associative
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|l1d policy=write-back
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|l2 cache=4 MiB
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|l2 break=2x2 MiB
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|l2 desc=16-way set associative
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|l2 policy=write-back
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}}

Revision as of 12:32, 11 December 2017

Edit Values
Celeron J4105
gemini lake (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberJ4105
Part NumberFH8068003067403
S-SpecSR3S4
MarketDesktop
IntroductionDecember 11, 2017 (announced)
December 11, 2017 (launched)
Release Price$107.00
ShopAmazon
General Specs
FamilyCeleron
Series4000
LockedYes
Frequency1,500 MHz
Turbo Frequency2,500 MHz (1 core)
Clock multiplier15
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureGoldmont Plus
Core NameGemini Lake
Core SteppingB0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP10 W
Packaging
PackageFCBGA-1090 (BGA)
Dimension25 mm x 24 mm
Contacts1090

Celeron J4105 is a quad-core 64-bit x86 desktop microprocessor introduced by Intel in 2017. This processor is based on Goldmont Plus microarchitecture and is manufactured on a 14 nm process. The J4105 operates at 1.5 GHz with a burst frequency of 2.5 GHz and a TDP of 10 W. This MPU incorporates Intel's UHD Graphics 600 GPU operating at 250 MHz with a burst frequency of 750 MHz.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Goldmont Plus § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$96 KiB
98,304 B
0.0938 MiB
4x24 KiB6-way set associativewrite-back
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  2x2 MiB16-way set associativewrite-back
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Facts about "Celeron J4105 - Intel"
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Celeron J4105 - Intel#package +
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +
clock multiplier15 +
core count4 +
core nameGemini Lake +
core steppingB0 +
designerIntel +
familyCeleron +
first announcedDecember 11, 2017 +
first launchedDecember 11, 2017 +
full page nameintel/celeron/j4105 +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description6-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateDecember 11, 2017 +
main imageFile:gemini lake (front).png +
manufacturerIntel +
market segmentDesktop +
max cpu count1 +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
microarchitectureGoldmont Plus +
model numberJ4105 +
nameCeleron J4105 +
packageFCBGA-1090 +
part numberFH8068003067403 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 107.00 (€ 96.30, £ 86.67, ¥ 11,056.31) +
s-specSR3S4 +
series4000 +
smp max ways1 +
tdp10 W (10,000 mW, 0.0134 hp, 0.01 kW) +
technologyCMOS +
thread count4 +
turbo frequency (1 core)2,500 MHz (2.5 GHz, 2,500,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +