Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i5/i5-9500"
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| − | '''Core i5-9500''' is a planned {{arch|64}} mid-range performance [[x86]] desktop processor by [[Intel]] set to be introduced in [[2018]]. The i5-9400 is fabricated on Intel's 2nd generation [[10 nm process|10nm+ process]] based on the {{intel|Ice Lake|l=arch}} microarchitecture. | + | '''Core i5-9500''' is a planned {{arch|64}} mid-range performance [[x86]] desktop processor by [[Intel]] set to be introduced in [[2018]]/2019. The i5-9400 is fabricated on Intel's 2nd generation [[10 nm process|10nm+ process]] based on the {{intel|Ice Lake|l=arch}} microarchitecture. |
Revision as of 09:29, 4 December 2017
Template:mpu Core i5-9500 is a planned 64-bit mid-range performance x86 desktop processor by Intel set to be introduced in 2018/2019. The i5-9400 is fabricated on Intel's 2nd generation 10nm+ process based on the Ice Lake microarchitecture.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
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Leaked Info! Some of the information presented in this article is solely based on leaks that were published online or obtained directly by WikiChip. It goes without saying that this information could change, be incomplete, wrong, or even made up. It's highly advised to wait for an official product announcement. |
Cache
- Main article: Ice Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i5-9500 - Intel"
| l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |