Semiconductor & Computer Engineering
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Difference between revisions of "Template:cache size"
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<table class="tl1" style="margin-left: 10px;"><!-- | <table class="tl1" style="margin-left: 10px;"><!-- | ||
-->{{#if: {{{l1 cache|}}} | <tr><th style="min-width: 35px;">L1$</th><td>[[l1$ size::{{{l1 cache}}}]]</td><td><table><!-- | -->{{#if: {{{l1 cache|}}} | <tr><th style="min-width: 35px;">L1$</th><td>[[l1$ size::{{{l1 cache}}}]]</td><td><table><!-- | ||
| − | -->{{#if: {{{l1i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">[[l1i$ size::{{{l1i cache}}}]]</td><td style="min-width: 75px;">{{{l1i break}}}</td><td style="min-width: 175px;">{{#if: {{{l1i desc|}}}|[[l1i$ description::{{{l1i desc}}}]]| }}</td><td>{{#if:{{{l1i policy|}}}|{{{l1i policy}}}| }}</td></tr> }}<!-- | + | -->{{#if: {{{l1i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">[[l1i$ size::{{{l1i cache}}}]]</td><td style="min-width: 75px;">{{{l1i break| }}}</td><td style="min-width: 175px;">{{#if: {{{l1i desc|}}}|[[l1i$ description::{{{l1i desc}}}]]| }}</td><td>{{#if:{{{l1i policy|}}}|{{{l1i policy}}}| }}</td></tr> }}<!-- |
| − | -->{{#if: {{{l1d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>[[l1d$ size::{{{l1d cache}}}]]</td><td style="min-width: 75px;">{{{l1d break}}}</td><td style="min-width: 175px;">{{#if:{{{l1d desc|}}}|[[l1d$ description::{{{l1d desc}}}]]| }}</td><td>{{#if:{{{l1d policy|}}}|{{{l1d policy}}}| }}</td></tr> }}<!-- | + | -->{{#if: {{{l1d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>[[l1d$ size::{{{l1d cache}}}]]</td><td style="min-width: 75px;">{{{l1d break| }}}</td><td style="min-width: 175px;">{{#if:{{{l1d desc|}}}|[[l1d$ description::{{{l1d desc}}}]]| }}</td><td>{{#if:{{{l1d policy|}}}|{{{l1d policy}}}| }}</td></tr> }}<!-- |
-->{{#if: {{#if:{{{l1i cache|}}}{{{l1d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l1 break}}}</td><td style="min-width: 175px;">{{#if: {{{l1 desc|}}} | [[l1$ description::{{{l1 desc}}}]] | }}</td><td>{{#if:{{{l1 policy|}}}|{{{l1 policy}}}| }}</td></tr> }}<!-- | -->{{#if: {{#if:{{{l1i cache|}}}{{{l1d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l1 break}}}</td><td style="min-width: 175px;">{{#if: {{{l1 desc|}}} | [[l1$ description::{{{l1 desc}}}]] | }}</td><td>{{#if:{{{l1 policy|}}}|{{{l1 policy}}}| }}</td></tr> }}<!-- | ||
--></table></td></tr>{{#if: {{{l2 cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- | --></table></td></tr>{{#if: {{{l2 cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- | ||
Latest revision as of 21:56, 2 November 2017
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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