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Difference between revisions of "freescale/qoriq/p1010"
< freescale/qoriq

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{{freescale title|QorIQ P1010}}
 
{{freescale title|QorIQ P1010}}
 
{{mpu
 
{{mpu
−
|name=P1010
+
|name=QorIQ P1010
 
|image=qoriq p1010.png
 
|image=qoriq p1010.png
 
|designer=Freescale
 
|designer=Freescale
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|series=P1
 
|series=P1
 
|frequency=667 MHz
 
|frequency=667 MHz
 +
|frequency 2=800 MHz
 
|isa=Power ISA v2.03
 
|isa=Power ISA v2.03
 
|isa family=Power
 
|isa family=Power
 
|microarch=e500
 
|microarch=e500
−
|core name=e500
+
|core name=e500 v2
 
|process=45 nm
 
|process=45 nm
 
|technology=CMOS
 
|technology=CMOS
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|core count=1
 
|core count=1
 
|thread count=1
 
|thread count=1
−
|power=5 W
+
|power=1.6 W
 
|tjunc min=0 °C
 
|tjunc min=0 °C
 
|tjunc max=125 °C
 
|tjunc max=125 °C
 
|package module 1={{packages/freescale/te-pbga-ii-689}}
 
|package module 1={{packages/freescale/te-pbga-ii-689}}
 +
|package module 2={{packages/freescale/te-pbga-425}}
 
}}
 
}}
 
'''QorIQ P1010''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 667 MHz and supports 32-bit DDR3-800 memory.
 
'''QorIQ P1010''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 667 MHz and supports 32-bit DDR3-800 memory.

Revision as of 23:02, 29 October 2017

Template:mpu QorIQ P1010 is a 32-bit embedded POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 667 MHz and supports 32-bit DDR3-800 memory.

Cache

Main article: e500 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Controllers1
Channels1
Width32 bit
Max Bandwidth2.98 GiB/s
3,051.52 MiB/s
3.2 GB/s
3,199.751 MB/s
0.00291 TiB/s
0.0032 TB/s
Bandwidth
Single 2.98 GiB/s

Expansions

  • 2x 10/100/1000 Eithernet with SGMII
  • 2x PCIe 1.0a controllers with 2 SerDes
  • 2x USB 2.0
  • SD/MMC
  • SPI
  • 2x I2C
  • UART
  • SEC 3.1 Security Acceleration

Block Diagram

qoriq p1010 block diagram.png

Documents

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Facts about "QorIQ P1010 - Freescale"
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has ecc memory supporttrue +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description8-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
max memory bandwidth2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) +
max memory channels1 +
supported memory typeDDR3-800 +