Semiconductor & Computer Engineering
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=== Identification === | === Identification === | ||
| + | [[File:QorIQ platform levels.png|right|600px]] | ||
Only applies to original QorIQ P & T series: | Only applies to original QorIQ P & T series: | ||
{{chip identification | {{chip identification | ||
Revision as of 01:30, 23 October 2017
| QorIQ | |
| Developer | Freescale, NXP |
| Manufacturer | IBM, TSMC |
| Type | System on Chips |
| Introduction | June 16, 2008 (announced) June 16, 2008 (launch) |
| Architecture | POWER & ARM Communication SoC |
| Word size | 32 bit 4 octets , 64 bit8 nibbles 8 octets
16 nibbles |
| Process | 45 nm 0.045 μm , 32 nm4.5e-5 mm 0.032 μm , 20 nm3.2e-5 mm 0.02 μm , 16 nm2.0e-5 mm 0.016 μm
1.6e-5 mm |
| Technology | CMOS |
| Clock | 533 MHz-2,000 MHz |
| Succession | |
| ← | |
| PowerQUICC | |
QorIQ (pronounced "Core IQ") is a family of ARM and POWER embedded and networking microprocessors designed and sold by NXP (formerly Freescale) since 2008 as a successor to the PowerQUICC family.
Overview
Introduced in 2008 by Freescale as a successor to the PowerQUICC family, then one of industry's most popular communications processors. Like the PowerQUICC brand, QorIQ spanned the entire range of products from low-power and low-cost to large multi-core designs. Original designs were based on the POWER architecture. In 2012 Freescale announced the Layerscape series that adopts the ARM architecture which Freescale/NXP has been using since.
Identification
Only applies to original QorIQ P & T series:
| Identification | ||||||||||||||
| QorIQ | P | 4 | 08 | 0 | ||||||||||
| QorIQ | P | 1 | 01 | 3 | ||||||||||
| Iteration/Version | ||||||||||||||
Core Count
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| Platform Level | ||||||||||||||
Technology Node
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Brand Name
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Series
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This section requires expansion; you can help adding the missing info. |
P Series
Announced in mid-2008, the QorIQ P-series are POWER-based microprocessors based on the e500 microarchitecture. Being the first Freescale multicore networking applications based on the 45 nm process, those parts offered a migration path for PowerQUICC II Pro and PowerQUICC III processor customers. All chips are fully software compatible with each other and existing PowerQUICC processors with multi-core parts supporting both symmetric and asymmetric multiprocessing.
P1
The P1 series are designed for low-power fan-less design designed to succeed previous models (e.g., PowerQUICC II Pro) with higher performance at the same power envelope. P1 parts are designed for the applications such as Ethernet switch controllers, gateways, wireless LAN access points, network printing/storage, and other networking devices with tight thermal constraints.
P2
The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.
See also
| designer | Freescale + and NXP + |
| first announced | June 16, 2008 + |
| first launched | June 16, 2008 + |
| full page name | nxp/qoriq + |
| instance of | system on a chip family + |
| main designer | Freescale + |
| manufacturer | IBM + and TSMC + |
| name | QorIQ + |
| process | 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) + |