Revision as of 13:35, 6 October 2017

Goldmont Plus (GLM+) is Intel's 14 nm microarchitecture of system on chips for the ultra-low power (ULP) devices serving as a successor to Goldmont. Goldmont Plus-based processors and SoCs are part of the Atom, Pentium, and Celeron families.

Codenames

Architecture

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Goldmont

• 4-way decode (from 3-way)^[1]
• VP9 10-bit Profile2 hardware decoding
• Integrated native HDMI 2.0 controller
• Integrated Intel Wireless-AC(Wi-Fi/BT CNVi)
• 4 MiB L2 cache per duplex (Up from 2 MiB)

Block Diagram

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Memory Hierarchy

• Cache
  • Hardware prefetchers
  • L1 Cache:
    • 32 KiB 8-way set associative instruction, 64 B line size
    • 24 KiB 6-way set associative data, 64 B line size
    • Per core
  • L2 Cache:
    • 4 MiB 16-way set associative, 64 B line size
    • Per 2 cores
  • L3 Cache:
    • No level 3 cache
  • RAM
    • Maximum of 1 GiB, 2 GiB, 4 GiB, 8 GiB
    • dual 32-bit channels, 1 or 2 ranks per channel

Multithreading

Goldmont Plus, like Goldmont has no support for Intel Hyper-Threading Technology.

Core

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1. ↑ https://patchwork.kernel.org/patch/9836747/