Semiconductor & Computer Engineering
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Discrepancies are for some of the non-AVX frequencies; my data for both sets of AVX frequencies are the same as yours. | Discrepancies are for some of the non-AVX frequencies; my data for both sets of AVX frequencies are the same as yours. | ||
From the edit history for that page, it appears that you entered those frequencies. | From the edit history for that page, it appears that you entered those frequencies. | ||
| − | Would you please check your sources and update the frequencies as appropriate? Thanks! | + | Would you please check your sources and update the frequencies as appropriate? Thanks! <small><span class="autosigned">— Preceding [[WikiChip:Signatures|unsigned]] comment added by [[User:ChuckEdN|ChuckEdN]] ([[User talk:ChuckEdN|talk]] • [[Special:Contributions/ChuckEdN|contribs]]) </span></small><!-- Template:Unsigned --> |
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| + | :Hey Chuck, | ||
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| + | : I follow the published frequencies from Intel's own datasheet, [https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-scalable-spec-update.pdf you can find them here]. I screenshot the appropriate row for the 6146 here https://i.imgur.com/xnvZD6s.png | ||
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| + | : That says the frequencies are "4.2, 4.2, 4.1, 4.1, 4.0, 4.0, 4.0, 4.0, 3.9, 3.9, 3.9, 3.9". which are the same ones we have for the [[Xeon Gold 6146]]. Are you saying those values are wrong? --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 13:18, 15 September 2017 (EDT) | ||
Revision as of 12:21, 15 September 2017
Goldmont
?> Hello World! <?
Re "Goldmont" article. You stuffed all my edits under "latency", even though most of them are about throughput. Throughput != latency. — Preceding unsigned comment added by 213.175.37.10 (talk • contribs)
- Yup my bad. It should've been throughput. I've changed it accordingly. --At32Hz (talk) 09:51, 27 October 2016 (EDT)
14 nm
"14nm lithography article" You reverted my edit about the sram density, while the Intel slide in the article clearly states that the sram density is higher than that of a logic tall cell. So do you claim the slide is wrong, or do i miss something obvious? — Preceding unsigned comment added by Nible (talk • contribs) 09:20, Jun 17, 2005 (UTC)
- Yea my mistake, I reverted it. I was going through new 14/7nm process info and mixed up some stuff. My bad. --At32Hz (talk) 18:01, 20 July 2017 (EDT)
Intel SoC diagrams
Hey, can you switch the Intel diagrams to correctly correspond to how the cache layout changes in Skylake & Kaby? As they shifted to the sides.--David (talk) 23:24, 7 September 2017 (EDT)
- Sure thing! --At32Hz (talk) 23:11, 8 September 2017 (EDT)
Please update non-AVX frequencies for 6146
I'm not at liberty to share the information, but I have an Intel document with frequencies for the Intel Xeon Gold 6146 processor. They differ from what is at intel/xeon_gold/6146#Frequencies. Discrepancies are for some of the non-AVX frequencies; my data for both sets of AVX frequencies are the same as yours. From the edit history for that page, it appears that you entered those frequencies. Would you please check your sources and update the frequencies as appropriate? Thanks! — Preceding unsigned comment added by ChuckEdN (talk • contribs)
- Hey Chuck,
- I follow the published frequencies from Intel's own datasheet, you can find them here. I screenshot the appropriate row for the 6146 here https://i.imgur.com/xnvZD6s.png
- That says the frequencies are "4.2, 4.2, 4.1, 4.1, 4.0, 4.0, 4.0, 4.0, 3.9, 3.9, 3.9, 3.9". which are the same ones we have for the Xeon Gold 6146. Are you saying those values are wrong? --At32Hz (talk) 13:18, 15 September 2017 (EDT)