From WikiChip
Difference between revisions of "renesas/r-car/m1s"
< renesas‎ | r-car

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| opengl es ver      = 2.0
 
| opengl es ver      = 2.0
 
| opengl ver          = 2.1
 
| opengl ver          = 2.1
}}
 
 
== Features ==
 
{{arm features
 
|thumb=No
 
|thumb2=Yes
 
|thumbee=Yes
 
|vfpv1=No
 
|vfpv2=No
 
|vfpv3=Yes
 
|vfpv3-d16=No
 
|vfpv3-f16=No
 
|vfpv4=No
 
|vfpv4-d16=No
 
|vfpv5=No
 
|neon=Yes
 
|jazelle=Yes
 
|wmmx=No
 
|wmmx2=No
 
 
}}
 
}}
  
 
== Block Diagram ==
 
== Block Diagram ==
 
: [[File:rcar m1s block.png|650px]]
 
: [[File:rcar m1s block.png|650px]]

Revision as of 02:18, 6 September 2017

Template:mpu R-Car M1S is a mid-range performance embedded single-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1S features a single SH-4A core operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.

Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-800
Supports ECCNo
Max Mem1 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth3.97 GiB/s
4,065.28 MiB/s
4.263 GB/s
4,262.755 MB/s
0.00388 TiB/s
0.00426 TB/s
Bandwidth
Single 3.97 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports2
Rate480 Mbps
UART
Ports8
SATA
Revision3.0
Ports1
I²C
Ports4

GP I/OYes
JTAGYes
  • MLB (MOST150) 6-Pin I/F
  • 2 x CAN 32 Message Buffers
  • MMC
  • 3 x SD

Graphics

  • 20MPoly/s; 1000MPix/s; 3.2GFlops/s

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX540
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency200 MHz
0.2 GHz
200,000 KHz

Standards
OpenGL2.1
OpenGL ES2.0

Block Diagram

rcar m1s block.png
Facts about "R-Car M1S - Renesas"
has ecc memory supportfalse +
integrated gpuPowerVR SGX540 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units2 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
max memory bandwidth3.97 GiB/s (4,065.28 MiB/s, 4.263 GB/s, 4,262.755 MB/s, 0.00388 TiB/s, 0.00426 TB/s) +
max memory channels1 +
supported memory typeDDR3-1066 + and DDR2-800 +