Revision as of 11:14, 4 September 2017

Template:mpu Ryzen Threadripper 1950X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor set to be introduced by AMD in mid-2017. The 1950X, which is based on their Zen microarchitecture, is fabricated on a 14 nm process. The 1950X operates at a base frequency of 3.4 GHz with a with a TDP of 180 W and a Boost frequency of 4.0 GHz. This MPU supports up to 1 TiB of quad-channel DDR4-2666 ECC memory.

As with the rest of the Threadripper family based on Zen, the 1950X consists of all four cores active in each CPU Complex (CCX) in each die. That is, four cores in each CCX in each of the dies are active for a total of sixteen cores in the entire package (4+4 [Die 1] + 4+4 [Die 2]).

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.5 MiB 1,536 KiB 1,572,864 B L1I$ 1 MiB 1,024 KiB 1,048,576 B 16x64 KiB 4-way set associative   L1D$ 512 KiB 524,288 B 0.5 MiB 16x32 KiB 8-way set associative write-back L2$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     16x512 KiB 8-way set associative write-back L3$ 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB     4x8 MiB 16-way set associative

Memory controller

This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM).

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Max Mem 1 TiB Controllers 4 Channels 4 Max Bandwidth 79.47 GiB/s 81,377.28 MiB/s 85.33 GB/s 85,330.263 MB/s 0.0776 TiB/s 0.0853 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s

Expansions

This processor includes 60 PCIe lanes with PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16). Note that 48 lanes are dedicated for multiple GPUs with the other 12 lanes for I/O.

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 3.0 Max Lanes 60 Configs x16, x8, x4, x1

• eMMC, LPC, SMBus, SPI/eSPI

Graphics

This processor has no integrated graphics.

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute SMT Simultaneous Multithreading AMD-Vi AMD-Vi (I/O MMU virtualization) AMD-V AMD Virtualization SenseMI SenseMI Technology XFR Extended Frequency Range

• This model has full XFR support, allowing for an additional +200 MHz
  0.2 GHz
  200,000 kHz
  
  boost frequency.