From WikiChip
Difference between revisions of "intel/celeron/807ue"
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+ | == Documents == | ||
+ | === Datasheet === | ||
+ | * [[:File:2nd-gen-core-family-mobile-vol-1-datasheet.pdf|Datasheet, Volume 1]] | ||
+ | * [[:File:2nd-gen-core-family-mobile-vol-2-datasheet.pdf|Datasheet, Volume 2]] | ||
+ | * [[:File:2nd-gen-core-mobile-ecc-datasheet-addendum.pdf|Datasheet Addendum for ECC models]] | ||
+ | === Other === | ||
+ | * [[:File:2nd-gen-core-mobile-thermal-guide.pdf|Thermal Design Guide for Embedded Applications]] | ||
+ | * [[:File:2nd-gen-core-family-mobile-specification-update.pdf|2nd Gen Core Mobile Specification Update]] |
Revision as of 15:30, 20 August 2017
Template:mpu Celeron 807UE is a single-core budget mobile embedded x86 microprocessor introduced by Intel in mid-2012. The Celeron 807UE, which is based on the Sandy Bridge microarchitecture and is manufactured on a 32 nm process, operates at 1 GHz with an ultra-low TDP of just 10 W. This chip incorporates Intel's HD Graphics integrated graphics operating at 350 MHz with a bust frequency of 800 MHz. This processor supports 4 GiB of single-channel DDR3-1333 ECC memory.
Contents
Cache
- Main article: Sandy Bridge § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
This processor has no PCIe lanes. As per datasheet:
The single core Celeron SKU Intel® Celeron® Processor 807UE does not support PCI Express in any configuration. All of the processor’s PCI Express lanes are disabled for both graphics and I/O.
Graphics
Integrated Graphics Information
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[Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | ✘ | Main | Main, High | Up to 80 Mbps | |||
MPEG-4 AVC (H.264) | Main | 4.1 | Up to 40 Mbps | Main, High | 4.1 | Up to 40 Mbps | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | Up to 40 Mbps |
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Documents
Datasheet
Other
Facts about "Celeron 807UE - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron 807UE - Intel#package + |
base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + |
bus links | 4 + |
bus rate | 5,000 MT/s (5 GT/s, 5,000,000 kT/s) + |
bus type | DMI 2.0 + |
chipset | Cougar Point + |
clock multiplier | 10 + |
core count | 1 + |
core family | 6 + |
core model | 42 + |
core name | Sandy Bridge M + |
core stepping | Q0 + |
core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + |
core voltage (min) | 0.3 V (3 dV, 30 cV, 300 mV) + |
cpuid | 0x206A7 + |
designer | Intel + |
device id | 0x0106 + |
die area | 131 mm² (0.203 in², 1.31 cm², 131,000,000 µm²) + |
family | Celeron + |
first announced | December 2011 + |
first launched | July 2012 + |
full page name | intel/celeron/807ue + |
has ecc memory support | true + |
has feature | Intel VT-x +, Flex Memory Access + and Enhanced SpeedStep Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics (Sandy Bridge) + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 6 + |
integrated gpu max frequency | 800 MHz (0.8 GHz, 800,000 KHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
ldate | July 2012 + |
manufacturer | Intel + |
market segment | Embedded + |
max cpu count | 1 + |
max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
max memory bandwidth | 9.93 GiB/s (10,168.32 MiB/s, 10.662 GB/s, 10,662.256 MB/s, 0.0097 TiB/s, 0.0107 TB/s) + |
max memory channels | 1 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Sandy Bridge + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | 807UE + |
name | Celeron 807UE + |
package | FCBGA-1023 + |
part number | AV8062701188200 + |
platform | Sandy Bridge M + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
s-spec | SR0NB + |
series | 800 + |
smp max ways | 1 + |
supported memory type | DDR3-1333 + and DDR3-1066 + |
tdp | 10 W (10,000 mW, 0.0134 hp, 0.01 kW) + |
technology | CMOS + |
thread count | 1 + |
transistor count | 504,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |