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Difference between revisions of "renesas/r-car/m1a"
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− | {{mpu}} | + | {{mpu |
+ | |name=R-Car M1A | ||
+ | |no image=Yes | ||
+ | |designer=Renesas | ||
+ | |designer 2=ARM Holdings | ||
+ | |manufacturer=TSMC | ||
+ | |model number=M1A | ||
+ | |part number=R8A77781 | ||
+ | |market=Embedded | ||
+ | |first announced=February 16, 2011 | ||
+ | |first launched=June, 2012 | ||
+ | |release price=$75 | ||
+ | |family=R-Car | ||
+ | |series=1st Gen | ||
+ | |frequency=800 MHz | ||
+ | |isa=ARMv7 | ||
+ | |isa family=ARM | ||
+ | |isa 2=SuperH | ||
+ | |isa 2 family=SuperH | ||
+ | |microarch=Cortex-A9 | ||
+ | |microarch 2=SH-4A | ||
+ | |core name=Cortex-A9 | ||
+ | |core name 2=SH-4A | ||
+ | |process=40 nm | ||
+ | |technology=CMOS | ||
+ | |word size=32 bit | ||
+ | |core count=2 | ||
+ | |thread count=2 | ||
+ | |max memory=1 GiB | ||
+ | |v core=1.2 V | ||
+ | |v io=3.3 V | ||
+ | |package module 1={{packages/renesas/fcbga-472}} | ||
+ | }} | ||
'''R-Car M1A''' is a mid-range performance embedded [[dual-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1A features a single {{armh|Cortex-A9|l=arch}} core and an additional {{renesas|SH-4A|l=arch}} core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory. | '''R-Car M1A''' is a mid-range performance embedded [[dual-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The M1A features a single {{armh|Cortex-A9|l=arch}} core and an additional {{renesas|SH-4A|l=arch}} core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory. |
Revision as of 09:58, 21 July 2017
Template:mpu R-Car M1A is a mid-range performance embedded dual-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1A features a single Cortex-A9 core and an additional SH-4A core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.
Facts about "R-Car M1A - Renesas"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | R-Car M1A - Renesas#package + |
base frequency | 800 MHz (0.8 GHz, 800,000 kHz) + |
core count | 2 + |
core name | Cortex-A9 + and SH-4A + |
core voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
designer | Renesas + and ARM Holdings + |
family | R-Car + |
first announced | February 16, 2011 + |
first launched | June 2012 + |
full page name | renesas/r-car/m1a + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | PowerVR SGX540 + |
integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
integrated gpu designer | Imagination Technologies + |
integrated gpu execution units | 2 + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | ARMv7 + and SuperH + |
isa family | ARM + and SuperH + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
ldate | June 2012 + |
manufacturer | TSMC + |
market segment | Embedded + |
max memory | 1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) + |
max memory bandwidth | 7.95 GiB/s (8,140.8 MiB/s, 8.536 GB/s, 8,536.248 MB/s, 0.00776 TiB/s, 0.00854 TB/s) + |
max memory channels | 2 + |
microarchitecture | Cortex-A9 + and SH-4A + |
model number | M1A + |
name | R-Car M1A + |
package | FCBGA-472 + |
part number | R8A77781 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + |
release price | $ 70.00 (€ 63.00, £ 56.70, ¥ 7,233.10) + |
series | 1st Gen + |
supported memory type | DDR2-800 + and DDR3-1066 + |
technology | CMOS + |
thread count | 2 + |
word size | 32 bit (4 octets, 8 nibbles) + |