From WikiChip
Difference between revisions of "intel/xeon silver/4108"
Line 178: | Line 178: | ||
== Frequencies == | == Frequencies == | ||
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
− | {{frequency table}} | + | {{frequency table |
+ | |freq_base=1,800 MHz | ||
+ | |freq_1=3,000 MHz | ||
+ | |freq_2=3,000 MHz | ||
+ | |freq_3=2,700 MHz | ||
+ | |freq_4=2,700 MHz | ||
+ | |freq_5=2,100 MHz | ||
+ | |freq_6=2,100 MHz | ||
+ | |freq_7=2,100 MHz | ||
+ | |freq_8=2,100 MHz | ||
+ | |freq_avx2_base=1,400 MHz | ||
+ | |freq_avx2_1=2,900 MHz | ||
+ | |freq_avx2_2=2,900 MHz | ||
+ | |freq_avx2_3=2,300 MHz | ||
+ | |freq_avx2_4=2,300 MHz | ||
+ | |freq_avx2_5=1,800 MHz | ||
+ | |freq_avx2_6=1,800 MHz | ||
+ | |freq_avx2_7=1,800 MHz | ||
+ | |freq_avx2_8=1,800 MHz | ||
+ | |freq_avx512_base=900 MHz | ||
+ | |freq_avx512_1=1,800 MHz | ||
+ | |freq_avx512_2=1,800 MHz | ||
+ | |freq_avx512_3=1,500 MHz | ||
+ | |freq_avx512_4=1,500 MHz | ||
+ | |freq_avx512_5=1,200 MHz | ||
+ | |freq_avx512_6=1,200 MHz | ||
+ | |freq_avx512_7=1,200 MHz | ||
+ | |freq_avx512_8=1,200 MHz | ||
+ | }} |
Revision as of 22:51, 17 July 2017
Template:mpu Xeon Silver 4108 is a 64-bit octa-core x86 dual-socket mid-range performance server microprocessor introduced by Intel in mid-2017. The Silver 4108, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 1.8 GHz with a TDP of 85 W and a turbo boost frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options
|
||||||||
|
Features
[Edit/Modify Supported Features]
Frequencies
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||
---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
Normal | 1,800 MHz | 3,000 MHz | 3,000 MHz | 2,700 MHz | 2,700 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz |
AVX2 | 1,400 MHz | 2,900 MHz | 2,900 MHz | 2,300 MHz | 2,300 MHz | 1,800 MHz | 1,800 MHz | 1,800 MHz | 1,800 MHz |
AVX512 | 900 MHz | 1,800 MHz | 1,800 MHz | 1,500 MHz | 1,500 MHz | 1,200 MHz | 1,200 MHz | 1,200 MHz | 1,200 MHz |
Facts about "Xeon Silver 4108 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4108 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
supported memory type | DDR4-2400 + |