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Difference between revisions of "intel/xeon platinum/8180"
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== Frequencies == | == Frequencies == | ||
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
− | {{frequency table}} | + | {{frequency table |
+ | |freq_base=2,500 MHz | ||
+ | |freq_1=3,800 MHz | ||
+ | |freq_2=3,800 MHz | ||
+ | |freq_3=3,600 MHz | ||
+ | |freq_4=3,600 MHz | ||
+ | |freq_5=3,500 MHz | ||
+ | |freq_6=3,500 MHz | ||
+ | |freq_7=3,500 MHz | ||
+ | |freq_8=3,500 MHz | ||
+ | |freq_9=3,500 MHz | ||
+ | |freq_10=3,500 MHz | ||
+ | |freq_11=3,500 MHz | ||
+ | |freq_12=3,500 MHz | ||
+ | |freq_13=3,500 MHz | ||
+ | |freq_14=3,500 MHz | ||
+ | |freq_15=3,500 MHz | ||
+ | |freq_16=3,500 MHz | ||
+ | |freq_17=3,500 MHz | ||
+ | |freq_18=3,500 MHz | ||
+ | |freq_19=3,500 MHz | ||
+ | |freq_20=3,500 MHz | ||
+ | |freq_21=3,300 MHz | ||
+ | |freq_22=3,300 MHz | ||
+ | |freq_23=3,300 MHz | ||
+ | |freq_24=3,300 MHz | ||
+ | |freq_25=3,200 MHz | ||
+ | |freq_26=3,200 MHz | ||
+ | |freq_27=3,200 MHz | ||
+ | |freq_28=3,200 MHz | ||
+ | }} |
Revision as of 20:39, 16 July 2017
Template:mpu Xeon Platinum 8180 is a 64-bit 28-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8180, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.5 GHz with a TDP of 205 W and a turbo boost frequency of up to 3.8 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Frequencies
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | ||
Normal | 2,500 MHz | 3,800 MHz | 3,800 MHz | 3,600 MHz | 3,600 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,200 MHz | 3,200 MHz | 3,200 MHz | 3,200 MHz |
Facts about "Xeon Platinum 8180 - Intel"