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'''Xeon Platinum 8158''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8158, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
 
'''Xeon Platinum 8158''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8158, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
  
== Features ==  
+
== Cache ==
{{x86 features
+
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
|real=Yes
+
{{cache size
|protected=Yes
+
|l1 cache=768 KiB
|smm=Yes
+
|l1i cache=384 KiB
|fpu=Yes
+
|l1i break=12x32 KiB
|x8616=Yes
+
|l1i desc=8-way set associative
|x8632=Yes
+
|l1d cache=384 KiB
|x8664=Yes
+
|l1d break=12x32 KiB
|nx=Yes
+
|l1d desc=8-way set associative
|mmx=Yes
+
|l1d policy=write-back
|emmx=Yes
+
|l2 cache=12 MiB
|sse=Yes
+
|l2 break=12x1 MiB
|sse2=Yes
+
|l2 desc=16-way set associative
|sse3=Yes
+
|l2 policy=write-back
|ssse3=Yes
+
|l3 cache=16.5 MiB
|sse41=Yes
+
|l3 break=12x1.375 MiB
|sse42=Yes
+
|l3 desc=11-way set associative
|sse4a=No
+
|l3 policy=write-back
|avx=Yes
 
|avx2=Yes
 
 
 
|abm=Yes
 
|tbm=No
 
|bmi1=Yes
 
|bmi2=Yes
 
|fma3=Yes
 
|fma4=No
 
|aes=Yes
 
|rdrand=Yes
 
|sha=No
 
|xop=No
 
|adx=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|tbt1=No
 
|tbt2=No
 
|tbmt3=No
 
|bpt=No
 
|eist=Yes
 
|sst=No
 
|flex=No
 
|fastmem=No
 
|isrt=No
 
|sba=No
 
|mwt=No
 
|sipp=No
 
|att=No
 
|ipt=No
 
|tsx=Yes
 
|txt=No
 
|ht=Yes
 
|vpro=Yes
 
|vtx=Yes
 
|vtd=Yes
 
|ept=Yes
 
|mpx=Yes
 
|sgx=No
 
|securekey=No
 
|osguard=Yes
 
|3dnow=No
 
|e3dnow=No
 
|smartmp=No
 
|powernow=No
 
|amdvi=No
 
|amdv=No
 
|rvi=No
 
|smt=No
 
|sensemi=No
 
|xfr=No
 
 
}}
 
}}

Revision as of 04:13, 12 July 2017

Template:mpu Xeon Platinum 8158 is a 64-bit dodeca-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8158, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back

L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back

L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB11-way set associativewrite-back
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +