From WikiChip
					
    Difference between revisions of "intel/xeon gold/6154"    
                	
														| Line 67: | Line 67: | ||
| |type=DDR4-2666 | |type=DDR4-2666 | ||
| |ecc=Yes | |ecc=Yes | ||
| − | |max mem= | + | |max mem=768 GiB | 
| − | |controllers= | + | |controllers=2 | 
| |channels=6 | |channels=6 | ||
| |max bandwidth=119.21 GiB/s | |max bandwidth=119.21 GiB/s | ||
| − | |bandwidth schan=19. | + | |bandwidth schan=19.87 GiB/s | 
| − | |bandwidth dchan=39. | + | |bandwidth dchan=39.74 GiB/s | 
| |bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
| |bandwidth hchan=119.21 GiB/s | |bandwidth hchan=119.21 GiB/s | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | {{expansions | ||
| + | | pcie revision      = 3.0 | ||
| + | | pcie lanes         = 48 | ||
| + | | pcie config        = x16 | ||
| + | | pcie config 2      = x8 | ||
| + | | pcie config 3      = x4 | ||
| }} | }} | ||
| Line 98: | Line 107: | ||
| |avx=Yes | |avx=Yes | ||
| |avx2=Yes | |avx2=Yes | ||
| − | + | |avx512f=Yes | |
| + | |avx512cd=Yes | ||
| + | |avx512er=No | ||
| + | |avx512pf=No | ||
| + | |avx512bw=Yes | ||
| + | |avx512dq=Yes | ||
| + | |avx512vl=Yes | ||
| + | |avx512ifma=No | ||
| + | |avx512vbmi=No | ||
| + | |avx5124fmaps=No | ||
| + | |avx5124vnniw=No | ||
| + | |avx512vpopcntdq=No | ||
| |abm=Yes | |abm=Yes | ||
| |tbm=No | |tbm=No | ||
| Line 113: | Line 133: | ||
| |f16c=Yes | |f16c=Yes | ||
| |tbt1=No | |tbt1=No | ||
| − | |tbt2= | + | |tbt2=Yes | 
| |tbmt3=No | |tbmt3=No | ||
| |bpt=No | |bpt=No | ||
| |eist=Yes | |eist=Yes | ||
| − | |sst= | + | |sst=Yes | 
| |flex=No | |flex=No | ||
| |fastmem=No | |fastmem=No | ||
| + | |ivmd=Yes | ||
| + | |intelnodecontroller=Yes | ||
| + | |intelnode=Yes | ||
| + | |kpt=Yes | ||
| + | |ptt=Yes | ||
| + | |mbe=Yes | ||
| |isrt=No | |isrt=No | ||
| |sba=No | |sba=No | ||
| Line 127: | Line 153: | ||
| |ipt=No | |ipt=No | ||
| |tsx=Yes | |tsx=Yes | ||
| − | |txt= | + | |txt=Yes | 
| |ht=Yes | |ht=Yes | ||
| |vpro=Yes | |vpro=Yes | ||
| Line 133: | Line 159: | ||
| |vtd=Yes | |vtd=Yes | ||
| |ept=Yes | |ept=Yes | ||
| − | |mpx= | + | |mpx=No | 
| |sgx=No | |sgx=No | ||
| |securekey=No | |securekey=No | ||
| − | |osguard= | + | |osguard=No | 
| |3dnow=No | |3dnow=No | ||
| |e3dnow=No | |e3dnow=No | ||
| Line 143: | Line 169: | ||
| |amdvi=No | |amdvi=No | ||
| |amdv=No | |amdv=No | ||
| + | |amdsme=No | ||
| + | |amdtsme=No | ||
| + | |amdsev=No | ||
| |rvi=No | |rvi=No | ||
| |smt=No | |smt=No | ||
Revision as of 01:19, 12 July 2017
Template:mpu Xeon Gold 6154 is a 64-bit 18-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6154, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3 GHz with a TDP of 200 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Contents
Cache
- Main article: Skylake § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||||||||||||||
| 
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Memory controller
|  | Integrated Memory Controller | |||||||||||||
| 
 | ||||||||||||||
Expansions
|  | Expansion Options | |||||||
| 
 | ||||||||
Features
[Edit/Modify Supported Features]
Facts about "Xeon Gold 6154  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6154 - Intel#io + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has advanced vector extensions 512 | true + | 
| has ecc memory support | true + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + | 
| has intel enhanced speedstep technology | true + | 
| has intel speed shift technology | true + | 
| has intel trusted execution technology | true + | 
| has intel turbo boost technology 2 0 | true + | 
| has intel vpro technology | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has transactional synchronization extensions | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| l1$ size | 1,152 KiB (1,179,648 B, 1.125 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 576 KiB (589,824 B, 0.563 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 576 KiB (589,824 B, 0.563 MiB) + | 
| l2$ description | 16-way set associative + | 
| l2$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + | 
| l3$ description | 11-way set associative + | 
| l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + | 
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + | 
| max memory channels | 6 + | 
| max pcie lanes | 48 + | 
| supported memory type | DDR4-2666 + | 
