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Difference between revisions of "intel/xeon gold/5122"
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|bandwidth qchan=71.53 GiB/s
 
|bandwidth qchan=71.53 GiB/s
 
|bandwidth hchan=107.3 GiB/s
 
|bandwidth hchan=107.3 GiB/s
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}}
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== Expansions ==
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{{expansions
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| pcie revision      = 3.0
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| pcie lanes        = 48
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| pcie config        = x16
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| pcie config 2      = x8
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| pcie config 3      = x4
 
}}
 
}}

Revision as of 19:55, 11 July 2017

Template:mpu Xeon Gold 5122 is a 64-bit quad-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5122, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.6 GHz with a TDP of 105 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

Cache

Main article: Skylake § Cache

The Xeon Gold 5122 features a considerably larger non-default 16.5 MiB of L3, a size that would normally be found on a 12-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back

L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  4x1 MiB16-way set associativewrite-back

L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 5122 - Intel#io +
has ecc memory supporttrue +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels6 +
max pcie lanes48 +
supported memory typeDDR4-2400 +