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Difference between revisions of "intel/xeon gold/5115"
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(Created page with "{{intel title|Xeon Gold 5115}} {{mpu |future=Yes |name=Xeon Gold 5115 |no image=Yes |designer=Intel |manufacturer=Intel |model number=5115 |part number=CD8067303535601 |market...")
 
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{{intel title|Xeon Gold 5115}}
 
{{intel title|Xeon Gold 5115}}
 
{{mpu
 
{{mpu
−
|future=Yes
 
 
|name=Xeon Gold 5115
 
|name=Xeon Gold 5115
−
|no image=Yes
+
|image=skylake sp (basic).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=5115
 
|model number=5115
 
|part number=CD8067303535601
 
|part number=CD8067303535601
 +
|s-spec=SR3GB
 
|market=Server
 
|market=Server
 +
|first announced=July 11, 2017
 +
|first launched=July 11, 2017
 +
|release price=$1221.00
 
|family=Xeon Gold
 
|family=Xeon Gold
 
|series=5000
 
|series=5000
 
|locked=Yes
 
|locked=Yes
 
|frequency=2,400 MHz
 
|frequency=2,400 MHz
 +
|turbo frequency1=3,200 MHz
 +
|clock multiplier=24
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
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|core name=Skylake SP
 
|core name=Skylake SP
 
|core family=6
 
|core family=6
 +
|core stepping=M0
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
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|core count=10
 
|core count=10
 
|thread count=20
 
|thread count=20
 +
|max cpus=4
 +
|max memory=768 GiB
 +
|tdp=85 W
 +
|tcase min=0 °C
 +
|tcase max=76 °C
 
|package module 1={{packages/intel/fclga-3647}}
 
|package module 1={{packages/intel/fclga-3647}}
 
}}
 
}}

Revision as of 19:21, 11 July 2017

Template:mpu Xeon Gold 5115 is a 64-bit deca-core x86 server microprocessor set to be introduced by Intel in July 2017. This processor operates at 2.4 GHz.

DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
655,360 B
0.625 MiB
L1I$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associative 
L1D$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associativewrite-back
L2$10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
  10x1 MiB16-way set associativewrite-back
L3$13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
  10x1.375 MiB11-way set associativewrite-back
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Facts about "Xeon Gold 5115 - Intel"
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l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description8-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description16-way set associative +
l2$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description11-way set associative +
l3$ size13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +